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st sitronix ST7773 262k color single-chip tft controller/driver ver. 2.0 1 2008-7-7 1. introduction ST7773 is a single-chip controller/driver for 262k-c olor, graphic type tft-lcd. it consists of 528 sour ce line and 220 gate line driver circuits. this chip can be connected to a microprocessor direct through serial peripheral i nterface (spi) or 8-bits/9-bits/16-bits/18-bits parallel interface. t he display data is stored in the on-chip display da ta ram (ddram) of 176x220x18 bits. it can perform display data ram rea d/write operation with no external operation clock to minimize power consumption. in addition, because of the integrated power supply circuits necessary to drive liquid cr ystal, it is possible to make a display system with fewer components. 2. features single chip tft-lcd controller/driver with ram on-chip display data ram (i.e. frame memory) - 176 x 220 x 18 = 696,960 bits lcd driver output circuits: - source outputs: 176 rgb channels - gate outputs: 220 channels display resolution - 176 (rgb) x 220 display colors (color mode) - full color: 262k, rgb=(666) max., idle mode off - color reduce: 8-color, rgb=(111), idle mode on programmable pixel color format (color depth) for various display data input format - 12-bit/pixel: rgb=(444) using whole frame memory - 16-bit/pixel: rgb=(565) using whole frame memory - 18-bit/pixel: rgb=(666) using whole frame memory various interfaces - parallel 8080-series mcu interface (8-bit, 9-bit, 16-bit & 18-bit) - 3-line serial interface display features - programmable partial display duty - line inversion, frame inversion - supporting mva type lc - support both normal-black & normal-white lc built-in circuits - dc/dc converter - adjustable vcom - 4 preset gamma curves (1.0, 1.8, 2.2 & 2.5) - oscillator for display clock generation - timing controller built-in nv memory for lcd initial register setting - 7-bits for id2 - 7-bits for vcom adjustment wide supply voltage range - i/o voltage (vddi to dgnd): 1.6v~3.3v - analog voltage (vdd to agnd): 2.7v~3.3v on-chip power system - source voltage (gvdd to agnd): 3.0v~5.0v - vcom high level (vcomh to agnd): 2.5v to 5.0v - vcom low level (vcoml to agnd): -2.5v to 0.0v - gate driver high level (vgh to agnd): +10.0v to 16v - gate driver low level (vgl to agnd): -13v to -5.5v operating temperature: -30c to +85c ST7773 8080 mcu interface: 8-bit/9-bit/16-bit/18-bit serial peripheral interface : 3-line sitronix technology corp. reserves the right to chan ge the contents in this document without prior noti ce
ST7773 ver. 2.0 2 2008-07-07 3. pad arrangement g1 g219 s2 im0 dummya extc vddio im1 im2 auto dgndo smy dgndo srgb vddio tpi[0] vddio dgndo vddio tpo[1] tpi[1] tpo[0] d6 d5 dgnd dgnd dgnd dgnd dgnd dgnd vddi vddi vddi vddi vdd vddi vddi vdd vdd vdd vdd vcc(o) vdd vdd vdd vcc vdd vcc vcc avdd(o) gvdd avdd(o) avdd avdd(o) avdd(o) avdd agnd avdd agnd agnd agnd agnd agnd agnd c11p agnd c11p c11p c12p c11n c11n c11n c12p c12p c12p vcl c23p c22n c22n c23n c23p c23n c23n vgh vgl vgl vgl vcom vgh vref vcom vcom vcom vcom ST7773 (bump-up) s528 g4 g2 s525 s526 g218 g220 g216 g214 vddio smx dgndo tpi[2] tpi[3] tpo[2] tpo[3] tpo[4] tpo[5] tpo[6] tpo[7] d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 dgndo d7 d4 d3 d2 d1 d0(sda) vddio dgndo osc te csx rdx wrx resx dgndo d/cx(sci) dgndo dgndo test dgnd dgnd vddi vdd vcc gvdd avdd c11p c11n c12n c12n c12n c12n vci1 vci1 vci1 vci1 c21p c21p c21p vcl(o) vcl vcl vcomh vcomh vcomh vcomh vcoml vcoml vcoml vcoml c22p c22p c22p c22n c23p vgh(o) vcom s527 g6 g8 s4 s1 s3 g5 g7 g3 g215 g217 g213 agnd agnd agnd agnd agnd c21n c21n c21n test test test test test test test test test test test test test test test test test test view point: bump view chip size (um): 17370x820 pad coordinate: pad center coordinate origin: chip center chip thickness (um): 300(typical) bump height (um): 15(typical) bump hardness (hv): 75(typical) pad arrangement (unit: um): output: pad no. 1 ~ 751 = 18 x 96 input: pad no. 752 ~ 947 = 50 x 96 70 96 50 50 alignment mark (unit: um): left align mark ( -8120.58,-300 ) left align mark ( 8080.6,-300 ) 30 40 30 alignment mark
ST7773 ver.2.0 3 2008-07-07 4. pad center coordinates unit: um pad no. pin name x y pad no. pin name x y 1 g220 7028 299 41 g140 6308 299 2 g218 7010 168 42 g138 6290 168 3 g216 6992 299 43 g136 6272 299 4 g214 6974 168 44 g134 6254 168 5 g212 6956 299 45 g132 6236 299 6 g210 6938 168 46 g130 6218 168 7 g208 6920 299 47 g128 6200 299 8 g206 6902 168 48 g126 6182 168 9 g204 6884 299 49 g124 6164 299 10 g202 6866 168 50 g122 6146 168 11 g200 6848 299 51 g120 6128 299 12 g198 6830 168 52 g118 6110 168 13 g196 6812 299 53 g116 6092 299 14 g194 6794 168 54 g114 6074 168 15 g192 6776 299 55 g112 6056 299 16 g190 6758 168 56 dummya 6038 168 17 g188 6740 299 57 g110 6020 299 18 g186 6722 168 58 g108 6002 168 19 g184 6704 299 59 g106 5984 299 20 g182 6686 168 60 g104 5966 168 21 g180 6668 299 61 g102 5948 299 22 g178 6650 168 62 g100 5930 168 23 g176 6632 299 63 g98 5912 299 24 g174 6614 168 64 g96 5894 168 25 g172 6596 299 65 g94 5876 299 26 g170 6578 168 66 g92 5858 168 27 g168 6560 299 67 g90 5840 299 28 g166 6542 168 68 g88 5822 168 29 g164 6524 299 69 g86 5804 299 30 g162 6506 168 70 g84 5786 168 31 g160 6488 299 71 g82 5768 299 32 g158 6470 168 72 g80 5750 168 33 g156 6452 299 73 g78 5732 299 34 g154 6434 168 74 g76 5714 168 35 g152 6416 299 75 g74 5696 299 36 g150 6398 168 76 g72 5678 168 37 g148 6380 299 77 g70 5660 299 38 g146 6362 168 78 g68 5642 168 39 g144 6344 299 79 g66 5624 299 40 g142 6326 168 80 g64 5606 168
ST7773 ver.2.0 2008-07-07 4 pad no. pin name x y pad no. pin name x y 81 g62 5588 299 121 s519 4275 168 82 g60 5570 168 122 s518 4257 299 83 g58 5552 299 123 s517 4239 168 84 g56 5534 168 124 s516 4221 299 85 g54 5516 299 125 s515 4203 168 86 g52 5498 168 126 s514 4185 299 87 g50 5480 299 127 s513 4167 168 88 g48 5462 168 128 s512 4149 299 89 g46 5444 299 129 s511 4131 168 90 g44 5426 168 130 s510 4113 299 91 g42 5408 299 131 s509 4095 168 92 g40 5390 168 132 s508 4077 299 93 g38 5372 299 133 s507 4059 168 94 g36 5354 168 134 s506 4041 299 95 g34 5336 299 135 s505 4023 168 96 g32 5318 168 136 s504 4005 299 97 g30 5300 299 137 s503 3987 168 98 g28 5282 168 138 s502 3969 299 99 g26 5264 299 139 s501 3951 168 100 g24 5246 168 140 s500 3933 299 101 g22 5228 299 141 s499 3915 168 102 g20 5210 168 142 s498 3897 299 103 g18 5192 299 143 s497 3879 168 104 g16 5174 168 144 s496 3861 299 105 g14 5156 299 145 s495 3843 168 106 g12 5138 168 146 s494 3825 299 107 g10 5120 299 147 s493 3807 168 108 g8 5102 168 148 s492 3789 299 109 g6 5084 299 149 s491 3771 168 110 g4 5066 168 150 s490 3753 299 111 g2 5048 299 151 s489 3735 168 112 s528 4437 299 152 s488 3717 299 113 s527 4419 168 153 s487 3699 168 114 s526 4401 299 154 s486 3681 299 115 s525 4383 168 155 s485 3663 168 116 s524 4365 299 156 s484 3645 299 117 s523 4347 168 157 s483 3627 168 118 s522 4329 299 158 s482 3609 299 119 s521 4311 168 159 s481 3591 168 120 s520 4293 299 160 s480 3573 299
ST7773 ver.2.0 2008-07-07 5 pad no. pin name x y pad no. pin name x y 161 s479 3555 168 201 s439 2835 168 162 s478 3537 299 202 s438 2817 299 163 s477 3519 168 203 s437 2799 168 164 s476 3501 299 204 s436 2781 299 165 s475 3483 168 205 s435 2763 168 166 s474 3465 299 206 s434 2745 299 167 s473 3447 168 207 s433 2727 168 168 s472 3429 299 208 s432 2709 299 169 s471 3411 168 209 s431 2691 168 170 s470 3393 299 210 s430 2673 299 171 s469 3375 168 211 s429 2655 168 172 s468 3357 299 212 s428 2637 299 173 s467 3339 168 213 s427 2619 168 174 s466 3321 299 214 s426 2601 299 175 s465 3303 168 215 s425 2583 168 176 s464 3285 299 216 s424 2565 299 177 s463 3267 168 217 s423 2547 168 178 s462 3249 299 218 s422 2529 299 179 s461 3231 168 219 s421 2511 168 180 s460 3213 299 220 s420 2493 299 181 s459 3195 168 221 s419 2475 168 182 s458 3177 299 222 s418 2457 299 183 s457 3159 168 223 s417 2439 168 184 s456 3141 299 224 s416 2421 299 185 s455 3123 168 225 s415 2403 168 186 s454 3105 299 226 s414 2385 299 187 s453 3087 168 227 s413 2367 168 188 s452 3069 299 228 s412 2349 299 189 s451 3051 168 229 s411 2331 168 190 s450 3033 299 230 s410 2313 299 191 s449 3015 168 231 s409 2295 168 192 s448 2997 299 232 s408 2277 299 193 s447 2979 168 233 s407 2259 168 194 s446 2961 299 234 s406 2241 299 195 s445 2943 168 235 s405 2223 168 196 s444 2925 299 236 s404 2205 299 197 s443 2907 168 237 s403 2187 168 198 s442 2889 299 238 s402 2169 299 199 s441 2871 168 239 s401 2151 168 200 s440 2853 299 240 s400 2133 299
ST7773 ver.2.0 2008-07-07 6 pad no. pin name x y pad no. pin name x y 241 s399 2115 168 281 s359 1395 168 242 s398 2097 299 282 s358 1377 299 243 s397 2079 168 283 s357 1359 168 244 s396 2061 299 284 s356 1341 299 245 s395 2043 168 285 s355 1323 168 246 s394 2025 299 286 s354 1305 299 247 s393 2007 168 287 s353 1287 168 248 s392 1989 299 288 s352 1269 299 249 s391 1971 168 289 s351 1251 168 250 s390 1953 299 290 s350 1233 299 251 s389 1935 168 291 s349 1215 168 252 s388 1917 299 292 s348 1197 299 253 s387 1899 168 293 s347 1179 168 254 s386 1881 299 294 s346 1161 299 255 s385 1863 168 295 s345 1143 168 256 s384 1845 299 296 s344 1125 299 257 s383 1827 168 297 s343 1107 168 258 s382 1809 299 298 s342 1089 299 259 s381 1791 168 299 s341 1071 168 260 s380 1773 299 300 s340 1053 299 261 s379 1755 168 301 s339 1035 168 262 s378 1737 299 302 s338 1017 299 263 s377 1719 168 303 s337 999 168 264 s376 1701 299 304 s336 981 299 265 s375 1683 168 305 s335 963 168 266 s374 1665 299 306 s334 945 299 267 s373 1647 168 307 s333 927 168 268 s372 1629 299 308 s332 909 299 269 s371 1611 168 309 s331 891 168 270 s370 1593 299 310 s330 873 299 271 s369 1575 168 311 s329 855 168 272 s368 1557 299 312 s328 837 299 273 s367 1539 168 313 s327 819 168 274 s366 1521 299 314 s326 801 299 275 s365 1503 168 315 s325 783 168 276 s364 1485 299 316 s324 765 299 277 s363 1467 168 317 s323 747 168 278 s362 1449 299 318 s322 729 299 279 s361 1431 168 319 s321 711 168 280 s360 1413 299 320 s320 693 299
ST7773 ver.2.0 2008-07-07 7 pad no. pin name x y pad no. pin name x y 321 s319 675 168 361 s279 -45 168 322 s318 657 299 362 s278 -63 299 323 s317 639 168 363 s277 -81 168 324 s316 621 299 364 s276 -99 299 325 s315 603 168 365 s275 -117 168 326 s314 585 299 366 s274 -135 299 327 s313 567 168 367 s273 -153 168 328 s312 549 299 368 s272 -171 299 329 s311 531 168 369 s271 -189 168 330 s310 513 299 370 s270 -207 299 331 s309 495 168 371 s269 -225 168 332 s308 477 299 372 s268 -243 299 333 s307 459 168 373 s267 -261 168 334 s306 441 299 374 s266 -279 299 335 s305 423 168 375 s265 -297 168 336 s304 405 299 376 dummya -315 299 337 s303 387 168 377 s264 -333 168 338 s302 369 299 378 s263 -351 299 339 s301 351 168 379 s262 -369 168 340 s300 333 299 380 s261 -387 299 341 s299 315 168 381 s260 -405 168 342 s298 297 299 382 s259 -423 299 343 s297 279 168 383 s258 -441 168 344 s296 261 299 384 s257 -459 299 345 s295 243 168 385 s256 -477 168 346 s294 225 299 386 s255 -495 299 347 s293 207 168 387 s254 -513 168 348 s292 189 299 388 s253 -531 299 349 s291 171 168 389 s252 -549 168 350 s290 153 299 390 s251 -567 299 351 s289 135 168 391 s250 -585 168 352 s288 117 299 392 s249 -603 299 353 s287 99 168 393 s248 -621 168 354 s286 81 299 394 s247 -639 299 355 s285 63 168 395 s246 -657 168 356 s284 45 299 396 s245 -675 299 357 s283 27 168 397 s244 -693 168 358 s282 9 299 398 s243 -711 299 359 s281 -9 168 399 s242 -729 168 360 s280 -27 299 400 s241 -747 299
ST7773 ver.2.0 2008-07-07 8 pad no. pin name x y pad no. pin name x y 401 s240 -765 168 441 s200 -1485 168 402 s239 -783 299 442 s199 -1503 299 403 s238 -801 168 443 s198 -1521 168 404 s237 -819 299 444 s197 -1539 299 405 s236 -837 168 445 s196 -1557 168 406 s235 -855 299 446 s195 -1575 299 407 s234 -873 168 447 s194 -1593 168 408 s233 -891 299 448 s193 -1611 299 409 s232 -909 168 449 s192 -1629 168 410 s231 -927 299 450 s191 -1647 299 411 s230 -945 168 451 s190 -1665 168 412 s229 -963 299 452 s189 -1683 299 413 s228 -981 168 453 s188 -1701 168 414 s227 -999 299 454 s187 -1719 299 415 s226 -1017 168 455 s186 -1737 168 416 s225 -1035 299 456 s185 -1755 299 417 s224 -1053 168 457 s184 -1773 168 418 s223 -1071 299 458 s183 -1791 299 419 s222 -1089 168 459 s182 -1809 168 420 s221 -1107 299 460 s181 -1827 299 421 s220 -1125 168 461 s180 -1845 168 422 s219 -1143 299 462 s179 -1863 299 423 s218 -1161 168 463 s178 -1881 168 424 s217 -1179 299 464 s177 -1899 299 425 s216 -1197 168 465 s176 -1917 168 426 s215 -1215 299 466 s175 -1935 299 427 s214 -1233 168 467 s174 -1953 168 428 s213 -1251 299 468 s173 -1971 299 429 s212 -1269 168 469 s172 -1989 168 430 s211 -1287 299 470 s171 -2007 299 431 s210 -1305 168 471 s170 -2025 168 432 s209 -1323 299 472 s169 -2043 299 433 s208 -1341 168 473 s168 -2061 168 434 s207 -1359 299 474 s167 -2079 299 435 s206 -1377 168 475 s166 -2097 168 436 s205 -1395 299 476 s165 -2115 299 437 s204 -1413 168 477 s164 -2133 168 438 s203 -1431 299 478 s163 -2151 299 439 s202 -1449 168 479 s162 -2169 168 440 s201 -1467 299 480 s161 -2187 299
ST7773 ver.2.0 2008-07-07 9 pad no. pin name x y pad no. pin name x y 481 s160 -2205 168 521 s120 -2925 168 482 s159 -2223 299 522 s119 -2943 299 483 s158 -2241 168 523 s118 -2961 168 484 s157 -2259 299 524 s117 -2979 299 485 s156 -2277 168 525 s116 -2997 168 486 s155 -2295 299 526 s115 -3015 299 487 s154 -2313 168 527 s114 -3033 168 488 s153 -2331 299 528 s113 -3051 299 489 s152 -2349 168 529 s112 -3069 168 490 s151 -2367 299 530 s111 -3087 299 491 s150 -2385 168 531 s110 -3105 168 492 s149 -2403 299 532 s109 -3123 299 493 s148 -2421 168 533 s108 -3141 168 494 s147 -2439 299 534 s107 -3159 299 495 s146 -2457 168 535 s106 -3177 168 496 s145 -2475 299 536 s105 -3195 299 497 s144 -2493 168 537 s104 -3213 168 498 s143 -2511 299 538 s103 -3231 299 499 s142 -2529 168 539 s102 -3249 168 500 s141 -2547 299 540 s101 -3267 299 501 s140 -2565 168 541 s100 -3285 168 502 s139 -2583 299 542 s99 -3303 299 503 s138 -2601 168 543 s98 -3321 168 504 s137 -2619 299 544 s97 -3339 299 505 s136 -2637 168 545 s96 -3357 168 506 s135 -2655 299 546 s95 -3375 299 507 s134 -2673 168 547 s94 -3393 168 508 s133 -2691 299 548 s93 -3411 299 509 s132 -2709 168 549 s92 -3429 168 510 s131 -2727 299 550 s91 -3447 299 511 s130 -2745 168 551 s90 -3465 168 512 s129 -2763 299 552 s89 -3483 299 513 s128 -2781 168 553 s88 -3501 168 514 s127 -2799 299 554 s87 -3519 299 515 s126 -2817 168 555 s86 -3537 168 516 s125 -2835 299 556 s85 -3555 299 517 s124 -2853 168 557 s84 -3573 168 518 s123 -2871 299 558 s83 -3591 299 519 s122 -2889 168 559 s82 -3609 168 520 s121 -2907 299 560 s81 -3627 299
ST7773 ver.2.0 2008-07-07 10 pad no. pin name x y pad no. pin name x y 561 s80 -3645 168 601 s40 -4365 168 562 s79 -3663 299 602 s39 -4383 299 563 s78 -3681 168 603 s38 -4401 168 564 s77 -3699 299 604 s37 -4419 299 565 s76 -3717 168 605 s36 -4437 168 566 s75 -3735 299 606 s35 -4455 299 567 s74 -3753 168 607 s34 -4473 168 568 s73 -3771 299 608 s33 -4491 299 569 s72 -3789 168 609 s32 -4509 168 570 s71 -3807 299 610 s31 -4527 299 571 s70 -3825 168 611 s30 -4545 168 572 s69 -3843 299 612 s29 -4563 299 573 s68 -3861 168 613 s28 -4581 168 574 s67 -3879 299 614 s27 -4599 299 575 s66 -3897 168 615 s26 -4617 168 576 s65 -3915 299 616 s25 -4635 299 577 s64 -3933 168 617 s24 -4653 168 578 s63 -3951 299 618 s23 -4671 299 579 s62 -3969 168 619 s22 -4689 168 580 s61 -3987 299 620 s21 -4707 299 581 s60 -4005 168 621 s20 -4725 168 582 s59 -4023 299 622 s19 -4743 299 583 s58 -4041 168 623 s18 -4761 168 584 s57 -4059 299 624 s17 -4779 299 585 s56 -4077 168 625 s16 -4797 168 586 s55 -4095 299 626 s15 -4815 299 587 s54 -4113 168 627 s14 -4833 168 588 s53 -4131 299 628 s13 -4851 299 589 s52 -4149 168 629 s12 -4869 168 590 s51 -4167 299 630 s11 -4887 299 591 s50 -4185 168 631 s10 -4905 168 592 s49 -4203 299 632 s9 -4923 299 593 s48 -4221 168 633 s8 -4941 168 594 s47 -4239 299 634 s7 -4959 299 595 s46 -4257 168 635 s6 -4977 168 596 s45 -4275 299 636 s5 -4995 299 597 s44 -4293 168 637 s4 -5013 168 598 s43 -4311 299 638 s3 -5031 299 599 s42 -4329 168 639 s2 -5049 168 600 s41 -4347 299 640 s1 -5067 299
ST7773 ver.2.0 2008-07-07 11 pad no. pin name x y pad no. pin name x y 641 g1 -5678 299 681 g81 -6398 299 642 g3 -5696 168 682 g83 -6416 168 643 g5 -5714 299 683 g85 -6434 299 644 g7 -5732 168 684 g87 -6452 168 645 g9 -5750 299 685 g89 -6470 299 646 g11 -5768 168 686 g91 -6488 168 647 g13 -5786 299 687 g93 -6506 299 648 g15 -5804 168 688 g95 -6524 168 649 g17 -5822 299 689 g97 -6542 299 650 g19 -5840 168 690 g99 -6560 168 651 g21 -5858 299 691 g101 -6578 299 652 g23 -5876 168 692 g103 -6596 168 653 g25 -5894 299 693 g105 -6614 299 654 g27 -5912 168 694 g107 -6632 168 655 g29 -5930 299 695 g109 -6650 299 656 g31 -5948 168 696 dummya -6668 168 657 g33 -5966 299 697 g111 -6686 299 658 g35 -5984 168 698 g113 -6704 168 659 g37 -6002 299 699 g115 -6722 299 660 g39 -6020 168 700 g117 -6740 168 661 g41 -6038 299 701 g119 -6758 299 662 g43 -6056 168 702 g121 -6776 168 663 g45 -6074 299 703 g123 -6794 299 664 g47 -6092 168 704 g125 -6812 168 665 g49 -6110 299 705 g127 -6830 299 666 g51 -6128 168 706 g129 -6848 168 667 g53 -6146 299 707 g131 -6866 299 668 g55 -6164 168 708 g133 -6884 168 669 g57 -6182 299 709 g135 -6902 299 670 g59 -6200 168 710 g137 -6920 168 671 g61 -6218 299 711 g139 -6938 299 672 g63 -6236 168 712 g141 -6956 168 673 g65 -6254 299 713 g143 -6974 299 674 g67 -6272 168 714 g145 -6992 168 675 g69 -6290 299 715 g147 -7010 299 676 g71 -6308 168 716 g149 -7028 168 677 g73 -6326 299 717 g151 -7046 299 678 g75 -6344 168 718 g153 -7064 168 679 g77 -6362 299 719 g155 -7082 299 680 g79 -6380 168 720 g157 -7100 168
ST7773 ver.2.0 2008-07-07 12 pad no. pin name x y pad no. pin name x y 721 g159 -7118 299 761 dgndo -7398.58 -299 722 g161 -7136 168 762 test -7328.58 -299 723 g163 -7154 299 763 vddio -7258.58 -299 724 g165 -7172 168 764 test -7188.58 -299 725 g167 -7190 299 765 test -7118.58 -299 726 g169 -7208 168 766 dgndo -7048.58 -299 727 g171 -7226 299 767 srgb -6978.58 -299 728 g173 -7244 168 768 smx -6908.58 -299 729 g175 -7262 299 769 smy -6838.58 -299 730 g177 -7280 168 770 vddio -6768.58 -299 731 g179 -7298 299 771 test -6698.58 -299 732 g181 -7316 168 772 test -6628.58 -299 733 g183 -7334 299 773 test -6558.58 -299 734 g185 -7352 168 774 test -6488.58 -299 735 g187 -7370 299 775 test -6418.58 -299 736 g189 -7388 168 776 dgndo -6348.58 -299 737 g191 -7406 299 777 test -6278.58 -299 738 g193 -7424 168 778 test -6208.58 -299 739 g195 -7442 299 779 vddio -6138.58 -299 740 g197 -7460 168 780 dgndo -6068.58 -299 741 g199 -7478 299 781 vddio -5998.58 -299 742 g201 -7496 168 782 tpi[0] -5928.58 -299 743 g203 -7514 299 783 tpi[1] -5858.58 -299 744 g205 -7532 168 784 tpi[2] -5788.58 -299 745 g207 -7550 299 785 tpi[3] -5718.58 -299 746 g209 -7568 168 786 tpo[0] -5648.58 -299 747 g211 -7586 299 787 tpo[1] -5578.58 -299 748 g213 -7604 168 788 tpo[2] -5508.58 -299 749 g215 -7622 299 789 tpo[3] -5438.58 -299 750 g217 -7640 168 790 tpo[4] -5368.58 -299 751 g219 -7658 299 791 tpo[5] -5298.58 -299 752 dummya -8028.58 -299 792 tpo[6] -5228.58 -299 753 extc -7958.58 -299 793 tpo[7] -5158.58 -299 754 vddio -7888.58 -299 794 test -5088.58 -299 755 im0 -7818.58 -299 795 d17 -5018.58 -299 756 im1 -7748.58 -299 796 d16 -4948.58 -299 757 im2 -7678.58 -299 797 d15 -4878.58 -299 758 test -7608.58 -299 798 d14 -4808.58 -299 759 test -7538.58 -299 799 d13 -4738.58 -299 760 auto -7468.58 -299 800 d12 -4668.58 -299
ST7773 ver.2.0 2008-07-07 13 pad no. pin name x y pad no. pin name x y 801 d11 -4598.58 -299 841 vddi -1798.58 -299 802 d10 -4528.58 -299 842 vddi -1728.58 -299 803 d9 -4458.58 -299 843 vddi -1658.58 -299 804 dgndo -4388.58 -299 844 vddi -1588.58 -299 805 d8 -4318.58 -299 845 vddi -1518.58 -299 806 d7 -4248.58 -299 846 vddi -1448.58 -299 807 d6 -4178.58 -299 847 vcc -673.45 -299 808 d5 -4108.58 -299 848 vcc -603.45 -299 809 d4 -4038.58 -299 849 vcc -533.45 -299 810 d3 -3968.58 -299 850 vcc -463.45 -299 811 d2 -3898.58 -299 851 vcco -393.45 -299 812 d1 -3828.58 -299 852 vdd 88.26 -299 813 d0(sda) -3758.58 -299 853 vdd 158.26 -299 814 vddio -3688.58 -299 854 vdd 228.26 -299 815 dgndo -3618.58 -299 855 vdd 298.26 -299 816 oscp -3548.58 -299 856 vdd 368.26 -299 817 tep -3478.58 -299 857 vdd 438.26 -299 818 csx -3408.58 -299 858 vdd 508.26 -299 819 rdx -3338.58 -299 859 vdd 578.26 -299 820 wrx -3268.58 -299 860 vdd 648.26 -299 821 test -3198.58 -299 861 vdd 718.26 -299 822 test -3128.58 -299 862 gvdd 788.26 -299 823 resx -3058.58 -299 863 gvdd 858.26 -299 824 dgndo -2988.58 -299 864 c11p 2232.71 -299 825 d/cx(sci) -2918.58 -299 865 c11p 2302.71 -299 826 dgndo -2848.58 -299 866 c11p 2372.71 -299 827 test -2778.58 -299 867 c11p 2442.71 -299 828 dgndo -2708.58 -299 868 c11n 2512.71 -299 829 test -2638.58 -299 869 c11n 2582.71 -299 830 test -2568.58 -299 870 c11n 2652.71 -299 831 test -2498.58 -299 871 c11n 2722.71 -299 832 dgnd -2428.58 -299 872 c12p 2792.71 -299 833 dgnd -2358.58 -299 873 c12p 2862.71 -299 834 dgnd -2288.58 -299 874 c12p 2932.71 -299 835 dgnd -2218.58 -299 875 c12p 3002.71 -299 836 dgnd -2148.58 -299 876 c12n 3072.71 -299 837 dgnd -2078.58 -299 877 c12n 3142.71 -299 838 dgnd -2008.58 -299 878 c12n 3212.71 -299 839 dgnd -1938.58 -299 879 c12n 3282.71 -299 840 vddi -1868.58 -299 880 avddo 3352.71 -299
ST7773 ver.2.0 2008-07-07 14 pad no. pin name x y pad no. pin name x y 881 avddo 3422.71 -299 921 vcoml 6222.71 -299 882 avddo 3492.71 -299 922 vcoml 6292.71 -299 883 avddo 3562.71 -299 923 vgl 6362.71 -299 884 avdd 3632.71 -299 924 vgl 6432.71 -299 885 avdd 3702.71 -299 925 vgl 6502.71 -299 886 avdd 3772.71 -299 926 vgho 6572.71 -299 887 avdd 3842.71 -299 927 vgh 6642.71 -299 888 agnd 3912.71 -299 928 vgh 6712.71 -299 889 agnd 3982.71 -299 929 c22p 6782.71 -299 890 agnd 4052.71 -299 930 c22p 6852.71 -299 891 agnd 4122.71 -299 931 c22p 6922.71 -299 892 agnd 4192.71 -299 932 c22n 6992.71 -299 893 agnd 4262.71 -299 933 c22n 7062.71 -299 894 agnd 4332.71 -299 934 c22n 7132.71 -299 895 agnd 4402.71 -299 935 c23p 7202.71 -299 896 agnd 4472.71 -299 936 c23p 7272.71 -299 897 agnd 4542.71 -299 937 c23p 7342.71 -299 898 agnd 4612.71 -299 938 c23n 7412.71 -299 899 agnd 4682.71 -299 939 c23n 7482.71 -299 900 agnd 4752.71 -299 940 c23n 7552.71 -299 901 vci1 4822.71 -299 941 vref 8172.06 -299 902 vci1 4892.71 -299 942 vcom 8242.06 -299 903 vci1 4962.71 -299 943 vcom 8312.06 -299 904 vci1 5032.71 -299 944 vcom 8382.06 -299 905 c21p 5102.71 -299 945 vcom 8452.06 -299 906 c21p 5172.71 -299 946 vcom 8522.06 -299 907 c21p 5242.71 -299 947 vcom 8592.06 -299 908 c21n 5312.71 -299 909 c21n 5382.71 -299 910 c21n 5452.71 -299 911 vclo 5522.71 -299 912 vcl 5592.71 -299 913 vcl 5662.71 -299 914 vcl 5732.71 -299 915 vcomh 5802.71 -299 916 vcomh 5872.71 -299 917 vcomh 5942.71 -299 918 vcomh 6012.71 -299 919 vcoml 6082.71 -299 920 vcoml 6152.71 -299
ST7773 ver. 2.0 2008-07-07 15 5. block diagram 528 source buffer dac level shifter data latch color conversion lut table display ram 176 x 220 x 18bits voltage reference gamma circuit gamma table display control 220 gate buffer level shifter gate decoder vcom generator osc booster 1/2/4 instruction register eeprom mcu if srgb gs wrx rdx csx dc/x (scl) im [2:0] extc smx smy d[17:0] vgl vgh vcl avdd vddi vdd vref gvdd vci1 vcomh vcoml vcom c11p c11n c12p c12n c21p c21n c22p c22n c23p c23n g1~g220 s1~s528
ST7773 ver. 2.0 2008-07-07 16 6. pin description 6.1 power supply pin name i/o description count connect pin vdd i power supply for analog, digital system and boo ster circuit. vdd vddi i power supply for i/o system. vddi agnd i system ground for analog system and booster ci rcuit. gnd dgnd i system ground for i/o system and digital syst em. gnd 6.2 interface logic pin name i/o description count connect pin im2 i mcu parallel interface bus and serial interface selec t im2=1, parallel interface im2=0, serial interface . 1 dgnd/vddi im1,im0 i - mcu parallel interface type selection -if not used, please fix this pin at vddi or dgnd l evel. im1 im0 parallel interface 0 0 mcu 8-bit parallel 0 1 mcu 16-bit parallel 1 0 mcu 9-bit parallel 1 1 mcu 18-bit parallel 2 dgnd/vddi resx i -this signal will reset the device and it must be a pplied to properly initialize the chip. -signal is active low. 1 mcu csx i -chip selection pin (low is enable). 1 mcu d/cx (sci) i -display data/command selection pin in mcu interfac e. -d/cx=1: display data or parameter. -d/cx=0: command data. -in serial interface, this is used as scl. 1 mcu rdx i -read enable in 8080 mcu parallel interface. -if not used, please connect this pin to vddi or dgn d. 1 mcu wrx i -write enable in mcu parallel interface. -if not used, please connect this pin to vddi or dgn d. 1 mcu osc o -monitoring pin of internal oscillator clock and is turned on/off by s/w command. -when this pin is inactive (function off), this pin is dgnd level. -if not used, please open this pin. 1 - d[17:0] i/o -d[17:0] are used as mcu parallel interface data bu s. -d0 is the serial input/output signal in serial int erface mode. -in serial interface, d[17:1] are not used and shou ld be connected to vddi or dgnd. 18 mcu te o -tearing effect output pin to synchronies mcu to fr ame rate, activated by s/w command. -when this pin is inactive, this pin is dgnd level. -if not used, please open this pin. 1 mcu note1. when in parallel mode, no use data pin must be connected to 1 or 0. note2.when csx=1,there is no influence to the paral ler and serial interface. note3. 1 =high= vddi level, 0 =low= dgnd lev el.
ST7773 ver. 2.0 2008-07-07 17 6.3 mode selection pin name i/o description count connect pin extc i -to use extended command set, please connect this p in to vddi. -during normal operation, please open this pin (int ernal r pull-down =2m ). extc enable/disable modification of extend command 0 only use default command set 1 use extended command set 1 vddi/dgnd srgb i -rgb arrangement selection pin for color filter desi gn. srgb rgb arrangement 0 s1, s2, s3 filter order = r , g , b 1 s1, s2, s3 filter order = b , g , r 1 vddi/dgnd smx i -scanning direction of source output selection pin. smx scanning direction of source output 0 s1->s528 1 s528->s1 1 vddi/dgnd smy i -scanning direction of gate output selection pin. smy scanning direction of gate output 0 g1->g220 1 g220->g1 1 vddi/dgnd auto i -please connect this pin to vddi. 1 vddi
ST7773 ver. 2.0 2008-07-07 18 6.4 driver output pin name i/o description count connect pin s1 to s528 o - source driver output pins. 528 - g1 to g220 o - gate driver output pins. 220 - vci1 i/o - a reference voltage for step-up circuit 1. - connect a capacitor for stabilization. 4 capacitor avdd i - power input pin for analog circuits. - in normal usage, connect it to avddo. 4 avddo avddo o - output of step-up circuit 1 - connect a capacitor for stabilization. 4 capacitor vcl i - power input pin for vcom circuit. - in normal usage, connect it to vclo. 3 vclo vclo o - a power output pin of step-up circuit 4. - when vcoml is higher than agnd, vclo=agnd. - connect a capacitor for stabilization. 1 capacitor vgh i - power input pin for gate driver circuit. - in normal usage, connect it to vgho. 2 vgho vgho o - positive output pin of the step-up circuit 2. - connect a capacitor for stabilization. 1 capacitor vgl i - power input pin for gate driver circuit. - negative output of the step-up circuit 2 is conne cted inside the driver. - connect a capacitor for stabilization. 3 vglo vref o - a reference voltage for power system. - connect a capacitor for stabilization. 1 capacitor gvdd o - a power output of grayscale voltage generator. - connect a capacitor for stabilization. - when internal gvdd generator is not used, connect an external power supply (avdd-0.5v) to this pin. 2 capacitor vcomh o - positive voltage output of vcom. - connect a capacitor for stabilization. 4 capacitor vcoml o - negative voltage output of vcom. - connect a capacitor for stabilization. 4 capacitor vcom o - a power supply for the tft-lcd common electrode. 6 common electrode c11p, c11n c12p, c12n o - capacitor connecting pins for step-up circuit 1 (for avddo) 16 step-up capacitor c21p, c21n c22p, c22n c23p, c23n o - capacitor connecting pins for step-up circuit 2 a nd 4 (for vgho, vglo, vclo) 18 step-up capacitor vddio o -vddi voltage output level for monitoring. 6 - dgndo o -dgnd voltage output level for monitoring. 9 - vcco o -monitoring pin of internal digital reference volta ge. -connect a capacitor for stabilization. 5 capacitor 6.5 test pin name i/o description count connect pin test i -please connect this pin to dgnd 19 dgnd tpi[3]~[0] i -please open these pins. 4 open tpo[7]~[0] o -please open these pins. 8 open dummy - -these pins are dummy (have no function inside). -can allow signal traces pass through these pads on tft glass. 4 open
ST7773 ver. 2.0 2008-07-07 19 7. driver electrical characteristics 7.1 absolute operation range item symbol rating unit supply voltage vdd - 0.3 ~ +4.6 v supply voltage (logic) vddi - 0.3 ~ +4.6 v supply voltage (digital) vcc -0.3 ~ +4.6 v driver supply voltage vgh-vgl -0.3 ~ +30.0 v logic input voltage range v in 0.3 ~ vddi + 0.3 v logic output voltage range v o 0.3 ~ vddi + 0.3 v operating temperature range t opr -30 ~ +85 storage temperature range t stg -40 ~ +125 note: if one of the above items is exceeded its max imum limitation momentarily, the quality of the pro duct may be degraded. absolute maximum limitation, therefore, sp ecify the values exceeding which the product may be physically damaged. be sure to use the product withi n the recommend range. 7.2 dc characteristic specification parameter symbol condition min typ max unit related pins power & operation voltage system voltage vdd operating voltage 2.7 2.8 3.3 v interface operation voltage vddi i/o supply voltage 1.6 1.8 3.3 v gate driver high voltage vgh 10 16 v gate driver low voltage vgl -13 -5.5 v gate driver supply voltage | vgh-vgl | 15.5 29.0 v input / output logic-high input voltage v ih 0.7vddi vddi v note 1 logic-low input voltage v il vss 0.3vddi v note 1 logic-high output voltage v oh i oh = -1.0ma 0.8vddi vddi v note 1 logic-low output voltage v ol i ol = +1.0ma vss 0.2vddi v note 1 input leakage current i il ioh = -1.0ma -1 +1 ua note 1 vcom voltage vcom high voltage vcomh ccom=22nf 2.5 5.0 v vcom low voltage vcoml ccom=22nf -2.5 0.0 v vcom amplitude vcomac |vcomh-vcoml| 4.0 6.0 v source driver gamma reference voltage gvdd 3.0 5.0 v source output settling time tr below with 99% precision 25 30 us note 2 output offset voltage v ofset 35 mv note 3 note 1: vddi=1.6 to 3.3v, vdd=2.7 to 3.3v, agnd=dgnd=0 v, t a =-25 note 2, source channel loading= 10pf/channel, gate channel loading=50pf/channel. note 3, the max. value is between measured point of gamma setting value. 7.3 power consumption ta=25 , frame rate = 60hz, the registers setting are ic d efault setting. current consumption typical maximum operation mode inversion mode image idd+iddi (ma) idd+iddi (ma) one line note 1 2.2 3.0 -normal mode one line note 2 2.2 3.0 note 1 1.3 1.6 -partial + idle mode (40 lines) one line note 2 1.3 1.6 -sleep-in mode n/a n/a 0.015 0.025 notes: 1. all pixels black. 2. all pixels white. typical case: worst case: ta = 25 ta = 25 vdd = 2.8 v vdd = 2.7~3.3v vddi = 1.8 v vddi = 1.6~3.3v
ST7773 ver. 2.0 2008-07-07 20 8. timing chart 8.1 parallel interface characteristics(8080-series mcu interface): 18, 16, 9 or 8-bits bus fig. 8.1.1 parallel interface timing characteristic s (8080-series mcu interface) signal symbol parameter min max unit description t ast address setup time 10 ns d/cx t aht address hold time (write/read) 15 ns - t chw chip select h pulse width 0 ns t cs chip select setup time (write) 30 ns t rcs chip select setup time (read id) 150 ns t rcsfm chip select setup time (read fm) 250 ns t csf chip select wait time (write/read) 10 ns csx t csh chip select hold time 10 ns -(3-transfer for one pixel) t wc write cycle 100 ns t wrh control pulse h duration 40 ns wrx t wrl control pulse l duration 30 ns 10mhz t rc read cycle (id) 160 ns t rdh control pulse h duration (id) 40 ns rdx (id) t rdl control pulse l duration (id) 100 ns when read id data t rcfm read cycle (fm) 400 ns t rdhfm control pulse h duration (fm) 40 ns rdx (fm) t rdlfm control pulse l duration (fm) 300 ns when read from frame memory t dst data setup time 10 ns t dht data hold time 15 ns t rat read access time (id) 100 ns t ratfm read access time (fm) 100 ns d[17:0] t odh output disable time 45 80 ns for maximum cl=30pf note 1: vddi=1.6 to 3.3v, vdd=2.7 to 3.3v, agnd=dgnd=0 v, ta= 25
ST7773 ver. 2.0 2008-07-07 21 fig. 8.1.2 rising and falling timing for input and output signal fig.8.1.3 chip selection (csx) timing fig. 8.1.4 write-to-read and read-to-write timing note: the rising time and falling time (tr, tf) of i nput signal are specified at 15 ns or less. logic h igh and low levels are specified as 30% and 70% of vddi for input signals.
ST7773 ver. 2.0 2008-07-07 22 8.3 serial interface characteristics (3-line serial ) csx v ih v il t chw t csh t oh t css scl sda sda (dout) t scc t scycw /t scycr t acc v ih v il v ih v il v ih v il v ih v il t sds t sdh t shw /t shr t slw /t slr fig. 8.3.1 3-line serial interface timing signal symbol parameter min max unit description t css chip select setup time 60 ns t csh chip select hold time 60 ns t scc chip select setup time 10 ns csx t chw chip select hold time 10 ns t scycw serial clock cycle (write) 65 ns t shw scl h pulse width (write) 20 ns t slw scl l pulse width (write) 40 ns t scycr serial clock cycle (read) 150 ns t shr scl h pulse width (read) 60 ns scl t slr scl l pulse width (read) 80 ns t sds data setup time 10 ns t sdh data hold time 15 ns t acc access time 80 ns sda (din) (dout) t oh output disable time 45 80 ns for maximum cl=30pf table 8.3: 3-line serial interface characteristics note 1: vddi=1.6 to 3.3v, vdd=2.7 to 3.3v, agnd=dgnd=0 v, ta=25 note 2: the rising time and falling time (tr, tf) o f input signal are specified at 15 ns or less. logi c high and low levels are specified as 30% and 70% of vddi for input signals.
ST7773 ver. 2.0 2008-07-07 23 9. function description 9.1 interface type selection the selection of given interfaces are done by setti ng im2, im1, and im0 pins as shown in following tab le. table 9.1.1 selection of mcu interface im2 im1 im0 interface read back selection 0 - - 3-line serial interface via the read instructi on 1 0 0 8080 mcu 8-bit parallel rdx strobe (8-bit rea d data and 8-bit read parameter) 1 0 1 8080 mcu 16-bit parallel rdx strobe (16-bit r ead data and 8-bit read parameter) 1 1 0 8080 mcu 9-bit parallel rdx strobe (9-bit rea d data and 8-bit read parameter) 1 1 1 8080 mcu 18-bit parallel rdx strobe (18-bit r ead data and 8-bit read parameter) table 9.1.2 pin connection according to various mcu interface im2 im1 im0 interface rdx wrx d/cx read back selection 0 - - 3-line serial interface note1 note1 scl d[17:1]: unused, d0: sda 1 0 0 8080 8-bit parallel rdx wrx d/cx d[17:8]: unused, d7-d0: 8-bit data 1 0 1 8080 16-bit parallel rdx wrx d/cx d[17:16]: unused, d15-d0: 16-bit data 1 1 0 8080 9-bit parallel rdx wrx d/cx d[17:9]: unused, d8-d0: 9-bit data 1 1 1 8080 18-bit parallel rdx wrx d/cx d17-d0: 18-bit data note 1. unused pins must be connected to dgnd or vdd i. 9.2 write cycle sequence the write cycle means that the host writes informat ion (command or/and data) to the display via the in terface. each write cycle (wrx high-low-high sequence) consists of 3 co ntrol signals (d/cx, rdx, wrx) and data signals (d[ 17:0]). d/cx bit is a control signal, which tells if the data is a c ommand or a data. the data signals are the command if the control signal is low (=0) and vice versa it is data (=1). fig. 9.2.1 8080-series wrx protocol note: wrx is an unsynchronized signal (it can be sto pped).
ST7773 ver. 2.0 2008-07-07 24 fig. 9.2.2 8080-series parallel bus protocol, write to register or display ram 9.3 read cycle sequence the read cycle (rdx high-low-high sequence) means t hat the host reads information from lcd driver via interface. the driver sends data (d[17:0]) to the host when there is a falling edge of rdx and the host reads data wh en there is a rising edge of rdx. fig. 9.2.3 8080-series rdx protocol note: rdx is an unsynchronized signal (it can be sto pped).
ST7773 ver. 2.0 2008-07-07 25 cmd dm pa cmd dm & data data data s p cmd dm pa cmd dm & data data data s p d[17:0] resx csx d/cx rdx wrx d[17:0] host d[17:0] host to lcd driver d[17:0] lcd to host 1 hi-z read parameter read display data cmd: write command code pa: parameter or display data signals on d[17:0], d/cx, r/wx, e pins during csx=1 are ignored. dm pa1 dm & data pa n-2 pa n-1 p s cmd cmd s p hi-z hi-z hi-z fig. 9.2.4 8080-series parallel bus protocol, read data from register or display ram
ST7773 ver. 2.0 2008-07-07 26 9.4 serial interface the selection of this interface is done by im2=low . the serial interface is either 3-lines/9-bits bi-di rectional interface for communication between the m icro controller and the lcd driver. the 3-lines serial interface use: csx (c hip enable), scl (serial clock) and sda (serial data input/output), serial clock (scl) is used for interface with mcu only, so it can be stopped when no communication is necessar y. 9.4.1 command write mode the write mode of the interface means the micro con troller writes commands and data to the lcd driver. 3-lines serial data packet contains a control bit d/cx and a transmissi on byte. any instruction can be sent in any order t o the driver. the msb is transmitted first. the serial interface is initi alized when csx is high. in this state, scl clock pu lse or sda data have no effect. a falling edge on csx enables the serial inte rface and indicates the start of data transmission. d/cx d7 d6 d5 d4 d3 d2 d1 d0 d/cx d7 d6 d5 d4 d3 d2 d1 d0 d/cx d7 d6 d5 d4 d3 d2 d1 d0 transmission byte (tb) may be command or data tb tb fig. 9.4.1 serial interface data stream format when csx is high, scl clock is ignored. during the high period of csx the serial interface is initializ ed. at the falling edge of csx, scl can be high or low (see fig 9.4.2). sda is sampled at the rising edge of scl. d/cx indicates w hether the byte is command (d/cx=0) or parameter/ram data (d/cx=1 ). d/cx is sampled when first rising edge of scl. i f csx stays low after the last bit of command/data byte, the se rial interface expects the d/cx bit of the next byt e at the next rising edge of scl. fig. 9.4.2 3-line serial interface write protocol ( write to register with control bit in transmission) 9.4.2 read functions the read mode of the interface means that the micro controller reads register value from the driver. t o achieve read function, the micro controller first has to send a command (read id or register command) and then the following byte is transmitted in the opposite direction. after that cs x is required to go to high before a new command is send (see the below figure). the driver samples the sda (input data) at r ising edge of scl, but shifts sda (output data) at the falling edge of scl. thus the micro controller is supported to read at the rising edge of scl. after the read status command has been sent, the sda l ine must be set to tri-state no later than at the f alling edge of scl of the last bit. serial protocol (for rdid1/rdid2/rdid3/0ah/0bh/0ch/0d h/0eh/0fh command: 8-bit read):
ST7773 ver. 2.0 2008-07-07 27 serial protocol (for rddid command: 24-bit read) serial protocol (for rddst command: 32-bit read) fig. 9.4.4 3-line serial interface read protocol
ST7773 ver. 2.0 2008-07-07 28 9.5 data transfer break and recovery if there is a break in data transmission by resx puls e, while transferring a command or frame memory dat a or multiple parameter command data, before bit d0 of the byte ha s been completed, then driver will reject the previ ous bits and have reset the interface such that it will be ready to r eceive command data again when the chip select line (csx) is next activated after resx have been high state. see the fol lowing example host (mcu to driver) fig. 9.5.1 serial bus protocol, write mode C interrupted by resx if there is a break in data transmission by csx puls e, while transferring a command or frame memory dat a or multiple parameter command data, before bit d0 of the byte ha s been completed, then driver will reject the previ ous bits and have reset the interface such that it will be ready to r eceive the same byte re-transmitted when the chip s elect line (csx) is next activated. see the following example fig. 9.5.2 serial bus protocol, write mode C interrupted by csx if 1, 2 or more parameter commands are being sent a nd a break occurs while sending any parameter befor e the last one and if the host then sends a new command rather tha n re-transmitting the parameter that was interrupte d, then the parameters that were successfully sent are stored a nd the parameter where the break occurred is reject ed. the interface is ready to receive next byte as shown below. fig.9.5.3 write interrupts recovery (serial interfa ce)
ST7773 ver. 2.0 2008-07-07 29 if a 2 or more parameter commands are being sent an d a break occurs by the other command before the la st one is sent, then the parameters that were successfully sent are stored and the other parameter of that command rem ains previous value. fig. 9.5.4 write interrupts recovery (both serial a nd parallel interface) 9.6 data transfer pause it will be possible when transferring a command, fr ame memory data or multiple parameter data to invok e a pause in the data transmission. if the chip select line is relea sed after a whole byte of a frame memory data or mu ltiple parameter data has been completed, then driver will wait and conti nue the frame memory data or parameter data transmi ssion from the point where it was paused. if the chip select line is released after a whole byte of a command has bee n completed, then the display module will receive either the command s parameters (if appropriate) or a new command when the chip select line is next enabled as shown below. this applies to the following 4 conditions: 1) command-pause-command 2) command-pause-parameter 3) parameter-pause-command 4) parameter-pause-parameter 9.6.1 serial interface pause fig. 9.6.1 serial interface pause protocol (pause b y csx)
ST7773 ver. 2.0 2008-07-07 30 9.6.2 parallel interface pause fig. 9.6.2 parallel bus pause protocol (paused by c sx) 9.7 data transfer modes the module has three kinds color modes for transfer ring data to the display ram. these are 12-bits col or per pixel, 16-bits color per pixel and 18-bits color per pixel. the da ta format is described for each interface. data can be downloaded to the frame memory by 2 methods. 9.7.1 method 1 the image data is sent to the frame memory in succe ssive frame writes, each time the frame memory is f illed, the frame memory pointer is reset to the start point and the next frame is written. 9.7.2 method 2 image data is sent and at the end of each frame mem ory download, a command is sent to stop frame memor y write. then start memory write command is sent, and a new frame is downloaded. note: 1) these apply to all data transfer color modes on both serial and parallel interfaces. 2) the frame memory can contain both odd and even n umber of pixels for both methods. only complete pix el data will be stored in the frame memory.
ST7773 ver. 2.0 2008-07-07 31 9.8 data color coding 9.8.1 8-bit parallel interface (im2, im1, im0= 100 ) different display data formats are available for th ree colors depth supported by listed below. - 4k colors, rgb 4,4,4-bit input, - 65k colors, rgb 5,6,5-bit input, . - 262k colors, rgb 6,6,6-bit input, 9.8.1.1 8-bit data bus for 12-bit/pixel (rgb 4-4-4-bit input), 4k-colors, 3ah= 03h there are 2 pixels (6 sub-pixels) per 3-bytes. note1. the data order is as follows, msb=d7, lsb=d0 and picture data is msb=bit 3, lsb=bit 0 for red, green and blue data. note 2. 3-time transfer is used to transmit 1 pixel data with the 12-bit color depth information. note 3. - = don't care - can be set to '0' or '1'
ST7773 ver. 2.0 2008-07-07 32 9.8.1.2 8-bit data bus for 16-bit/pixel (rgb 5-6-5-bit input), 65k-colors , 3ah= 05h there is 1 pixel (3 sub-pixels) per 2-bytes. r1, bit 4 g1, bit 2 0 r1, bit 3 g1, bit 1 0 r1, bit 2 g1, bit 0 1 r1, bit 1 b1, bit 4 0 r1, bit 0 b1, bit 3 1 g1, bit 5 b1, bit 2 1 g1, bit 4 b1, bit 1 0 g1, bit 3 b1, bit 0 0 8080-series control pins 6800-series control pins resx im[2:0] csx d/cx ? 1 ? ? 100 ? wrx rdx ? 1 ? r/wx e d7 d6 d5 d4 d3 d2 d1 d0 pixeln pixeln+1 look-up table for 65k color data mapping (16 bits to 18 bits) 16bits 16bits r1 g1 b1 r2 g2 b2 r3 g3 b3 18bits framememory r2, bit 4 g2, bit 2 r2, bit 3 g2, bit 1 r2, bit 2 g2, bit 0 r2, bit 1 b2, bit 4 r2, bit 0 b2, bit 3 g2, bit 5 b2, bit 2 g2, bit 4 b2, bit 1 g2, bit 3 b2, bit 0 ? 0 ? note1. the data order is as follows, msb=d7, lsb=d0 and picture data is msb=bit 5, lsb=bit 0 for green and msb=bit 4, lsb=bit 0 for red and blue data. note 2.2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information. note 3. - = don't care - can be set to '0' or '1'
ST7773 ver. 2.0 2008-07-07 33 9.8.1.3 8-bit data bus for 18-bit/pixel (rgb 6-6-6-bit input), 262k-color s, 3ah= 06h there is 1 pixel (3 sub-pixels) per 3-bytes. r1, bit 4 0 r1, bit 3 0 r1, bit 2 1 r1, bit 1 0 r1, bit 0 1 r1, bit 5 1 - - 0 - - 0 8080-series control pins 6800-series control pins resx im[2:0] csx d/cx ? 1 ? ? 100 ? wrx rdx ? 1 ? r/wx e d7 d6 d5 d4 d3 d2 d1 d0 pixeln pixeln+1 18bits 18bits r1 g1 b1 r2 g2 b2 r3 g3 b3 framememory - - - - g1, bit 4 g1, bit 3 g1, bit 2 g1, bit 1 g1, bit 0 g1, bit 5 b1, bit 4 b1, bit 3 b1, bit 2 b1, bit 1 b1, bit 0 b1, bit 5 r2, bit 4 r2, bit 3 r2, bit 2 r2, bit 1 r2, bit 0 r2, bit 5 ? 0 ? note1. the data order is as follows, msb=d7, lsb=d0 and picture data is msb=bit 5, lsb=bit 0 for red, green and blue data. note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. note 3. - = don't care - can be set to '0' or '1'
ST7773 ver. 2.0 2008-07-07 34 9.8.2 16-bit parallel interface (im2,im1, im0= 101 ) different display data formats are available for th ree colors depth supported by listed below. - 4k colors, rgb 4,4,4-bit input - 65k colors, rgb 5,6,5-bit input - 262k colors, rgb 6,6,6-bit input 9.8.2.1 16-bit data bus for 12-bit/pixel (rgb 4-4-4-bit input), 4k-colors, 3ah= 03h there is 1 pixel (3 sub-pixels) per 1 bytes, 12-bit /pixel. note1. the data order is as follows, msb=d11, lsb=d0 an d picture data is msb=bit 3, lsb=bit 0 for red, green an d blue data. note 2.1-times transfer (d11 to d0) is used to tran smit 1 pixel data with the 12-bit color depth infor mation.
ST7773 ver. 2.0 2008-07-07 35 9.8.2.2 16-bit data bus for 16-bit/pixel (rgb 5-6-5-bit input), 65k-colors , 3ah= 05h there is 1 pixel (3 sub-pixels) per 1 bytes, 16-bit /pixel. note1. the data order is as follows, msb=d15, lsb=d0 an d picture data is msb=bit 5, lsb=bit 0 for green, and msb=b it 4, lsb=bit 0 for red and blue data. note 2.1-times transfer (d15 to d0) is used to tran smit 1 pixel data with the 16-bit color depth infor mation. note 3. - = don't care - can be set to '0' or '1'
ST7773 ver. 2.0 2008-07-07 36 9.8.2.3 16-bit data bus for 18-bit/pixel (rgb 6-6-6-bit input), 262k-color s, 3ah= 06h there are 2 pixel (6 sub-pixels) per 3 bytes, 18-bi t/pixel. note1. the data order is as follows, msb=d15, lsb=d0 an d picture data is msb=bits 5, lsb=bit 0 for red, green an d blue data. note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. note 3. - = don't care - can be set to '0' or '1'
ST7773 ver. 2.0 2008-07-07 37 9.8.3 9-bit parallel interface (im2, im1, im0=110 ) different display data formats are available for th ree colors depth supported by listed below. - 262k colors, rgb 6,6,6-bit input r1, bit 4 0 r1, bit 3 0 r1, bit 2 1 r1, bit 1 0 r1, bit 0 1 r1, bit 5 1 0 0 8080-series control pins 6800-series control pins resx im[2:0] csx d/cx ? 1 ? ? 110 ? wrx rdx ? 1 ? r/wx e d7 d6 d5 d4 d3 d2 d1 d0 pixeln pixeln+1 18bits 18bits r1 g1 b1 r2 g2 b2 r3 g3 b3 framememory g1, bit 4 g1, bit 3 g1, bit 2 g1, bit 1 g1, bit 0 b1, bit 4 b1, bit 3 b1, bit 2 b1, bit 1 b1, bit 0 b1, bit 5 r2, bit 4 r2, bit 3 r2, bit 2 r2, bit 1 r2, bit 0 r2, bit 5 ? 0 ? - g1, bit 5 d8 g2, bit 4 g2, bit 3 g2, bit 5 b2, bit 4 b2, bit 3 b2, bit 2 b2, bit 1 b2, bit 0 b2, bit 5 g2, bit 2 g2, bit 1 g2, bit 0 note1. the data order is as follows, msb=d8, lsb=d0 and picture data is msb=bit 5, lsb=bit 0 for red, green and blue data. note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. note 3. - = don't care - can be set to '0' or '1'
ST7773 ver. 2.0 2008-07-07 38 9.8.4 18-bit parallel interface (im2, im1, im0=111 ) different display data formats are available for th ree colors depth supported by listed below. - 4k colors, rgb 4,4,4-bit input - 65k colors, rgb 5,6,5-bit input - 262k colors, rgb 6,6,6-bit input. 9.8.4.1 18-bit data bus for 12-bit/pixel (rgb 4-4-4-bit input), 4k-colors, 3ah=03h there are 1 pixel (3 sub-pixels) per 1 byte, 12-bit /pixel. - - - - g1, bit 3 - g1, bit 2 - g1, bit 1 - g1, bit 0 - 8080-series control pins 6800-series control pins resx im[2:0] csx d/cx ? 1 ? ? 111 ? wrx rdx ? 1 ? r/wx e d15 d14 d13 d12 d11 d10 d9 d8 pixeln pixeln+1 12bits 12bits r1 g1 b1 r2 g2 b2 r3 g3 b3 18bits framememory r1, bit 3 0 r1, bit 2 0 r1, bit 1 1 r1, bit 0 0 1 1 0 0 d7 d6 d5 d4 d3 d2 d1 d0 - - - - b1, bit 3 b1, bit 2 b1, bit 1 b1, bit 0 g2, bit 3 g2, bit 2 g2, bit 1 g2, bit 0 r2, bit 3 r2, bit 2 r2, bit 1 r2, bit 0 - - - - b2, bit 3 b2, bit 2 b2, bit 1 b2, bit 0 g3, bit 3 g3, bit 2 g3, bit 1 g3, bit 0 r3, bit 3 r3, bit 2 r3, bit 1 r3, bit 0 - - - - b3, bit 3 b3, bit 2 b3, bit 1 b3, bit 0 g4, bit 3 g4, bit 2 g4, bit 1 g4, bit 0 r4, bit 3 r4, bit 2 r4, bit 1 r4, bit 0 - - - - b4, bit 3 b4, bit 2 b4, bit 1 b4, bit 0 pixeln+2 pixeln+3 look-up table for 4096 color data mapping (12 bits to 18 bits) ? 0 ? - - d17 - - - - - - - - d16
ST7773 ver. 2.0 2008-07-07 39 note1. the data order is as follows, msb=d11, lsb=d0 an d picture data is msb=bit 3, lsb=bit 0 for red, green an d blue data. note 2.1-times transfer is used to transmit 1 pixel data with the 12-bit color depth information. 9.8.4.2 18-bit data bus for 16-bit/pixel (rgb 5-6-5-bit input), 65k-colors , 3ah=05h there are 1 pixel (3 sub-pixels) per 1 byte, 16-bit /pixel. - - - - g1, bit 3 - g1, bit 2 - g1, bit 1 - g1, bit 0 - 8080-series control pins 6800-series control pins resx im[2:0] csx d/cx ? 1 ? ? 111 ? wrx rdx ? 1 ? r/wx e d15 d14 d13 d12 d11 d10 d9 d8 pixeln pixeln+1 16bits 16bits r1 g1 b1 r2 g2 b2 r3 g3 b3 18bits framememory r1, bit 3 0 r1, bit 2 0 r1, bit 1 1 r1, bit 0 0 1 1 0 0 d7 d6 d5 d4 d3 d2 d1 d0 b1, bit 3 b1, bit 2 b1, bit 1 b1, bit 0 g2, bit 3 g2, bit 2 g2, bit 1 g2, bit 0 r2, bit 3 r2, bit 2 r2, bit 1 r2, bit 0 b2, bit 3 b2, bit 2 b2, bit 1 b2, bit 0 g3, bit 3 g3, bit 2 g3, bit 1 g3, bit 0 r3, bit 3 r3, bit 2 r3, bit 1 r3, bit 0 b3, bit 3 b3, bit 2 b3, bit 1 b3, bit 0 g4, bit 3 g4, bit 2 g4, bit 1 g4, bit 0 r4, bit 3 r4, bit 2 r4, bit 1 r4, bit 0 b4, bit 3 b4, bit 2 b4, bit 1 b4, bit 0 pixeln+2 pixeln+3 look-up table for 65k color data mapping (16 bits to 18 bits) ? 0 ? - - d17 - - - - - - - - d16 r1, bit 4 r2, bit 4 r3, bit 4 r4, bit 4 g1, bit 5 g1, bit 4 g2, bit 5 g2, bit 4 g3, bit 5 g3, bit 4 g4, bit 5 g4, bit 4 b1, bit 4 b2, bit 4 b3, bit 4 b4, bit 4 note1. the data order is as follows, msb=d15, lsb=d0 an d picture data is msb=bit 5, lsb=bit 0 for green, and msb=b it 4, lsb=bit 0 for red and blue data.
ST7773 ver. 2.0 2008-07-07 40 note 2.1-times transfer is used to transmit 1 pixel data with the 16-bit color depth information. 9.8.4.3 18-bit data bus for 18-bit/pixel (rgb 6-6-6-bit input), 262k-color s, 3ah=06h there are 1 pixel (3 sub-pixels) per 1 bytes, 18-bi t/pixel. - - - - g1, bit 3 - g1, bit 2 - g1, bit 1 - g1, bit 0 - 8080-series control pins 6800-series control pins resx im[2:0] csx d/cx ? 1 ? ? 111 ? wrx rdx ? 1 ? r/wx e d15 d14 d13 d12 d11 d10 d9 d8 pixeln pixeln+1 18bits 18bits r1 g1 b1 r2 g2 b2 r3 g3 b3 framememory r1, bit 3 0 r1, bit 2 0 r1, bit 1 1 r1, bit 0 0 1 1 0 0 d7 d6 d5 d4 d3 d2 d1 d0 b1, bit 3 b1, bit 2 b1, bit 1 b1, bit 0 g2, bit 3 g2, bit 2 g2, bit 1 g2, bit 0 r2, bit 3 r2, bit 2 r2, bit 1 r2, bit 0 b2, bit 3 b2, bit 2 b2, bit 1 b2, bit 0 g3, bit 3 g3, bit 2 g3, bit 1 g3, bit 0 r3, bit 3 r3, bit 2 r3, bit 1 r3, bit 0 b3, bit 3 b3, bit 2 b3, bit 1 b3, bit 0 g4, bit 3 g4, bit 2 g4, bit 1 g4, bit 0 r4, bit 3 r4, bit 2 r4, bit 1 r4, bit 0 b4, bit 3 b4, bit 2 b4, bit 1 b4, bit 0 pixeln+2 pixeln+3 ? 0 ? - - d17 d16 r1, bit 4 r2, bit 4 r3, bit 4 r4, bit 4 g1, bit 5 g1, bit 4 g2, bit 5 g2, bit 4 g3, bit 5 g3, bit 4 g4, bit 5 g4, bit 4 b1, bit 4 b2, bit 4 b3, bit 4 b4, bit 4 r1, bit 5 r2, bit 5 r3, bit 5 r4, bit 5 b1, bit 5 b2, bit 5 b3, bit 5 b4, bit 5 note1. the data order is as follows, msb=d17, lsb=d0 an d picture data is msb=bit 5, lsb=bit 0 for read, green a nd blue data. note 2.1-times transfer (d17o d0) is used to transm it 1 pixel data with the 18-bit color depth informa tion. n
ST7773 ver. 2.0 2008-07-07 41 9.8.5 3-line serial interface different display data formats are available for th ree colors depth supported by the lcm listed below. 4k colors, rgb 4-4-4-bit input 65k colors, rgb 5-6-5-bit input 262k colors, rgb 6-6-6-bit input 9.8.5.1 write data for 12-bit/pixel (rgb 4-4-4-bit input), 4k-colors, 3ah=03h note 1. pixel data with the 12-bit color depth info rmation note 2. the most significant bits are: rx3, gx3 and bx3 note 3. the least significant bits are: rx0, gx0 an d bx0 9.8.5.2 write data for 16-bit/pixel (rgb 5-6-5-bit input), 65k-colors, 3ah=05h note 1. pixel data with the 16-bit color depth info rmation note 2. the most significant bits are: rx4, gx5 and bx4 note 3. the least significant bits are: rx0, gx0 an d bx0
ST7773 ver. 2.0 2008-07-07 42 9.8.5.3 write data for 18-bit/pixel (rgb 6-6-6-bit input), 262k-colors, 3ah=06h note 1. pixel data with the 18-bit color depth info rmation note 2. the most significant bits are: rx5, gx5 and bx5 note 3. the least significant bits are: rx0, gx0 an d bx0
ST7773 ver. 2.0 2008-07-07 43 9.9 display data ram 9.9.1 configuration the display module has an integrated 176x220x18-bit graphic type static ram. this 696,960-bit memory al lows to store on-chip a 176xrgbx220 image with an 18-bpp resoluti on (262k-color). there will be no abnormal visible effect on the dis play when there is a simultaneous panel read and in terface read or write to the same location of the frame memory. fig. 9.9.1 display data ram organization
ST7773 ver. 2.0 2008-07-07 44 9.9.2 memory to display address mapping -------- gate out s1 s2 s3 s4 s5 s6 -------- s523 s524 s525 s526 s527 s528 my=' 0 ' my=' 1 ' ml=' 0 ' ml=' 1 ' 1 0 219 r0 g0 b0 r1 g1 b1 -------- r174 g174 b174 r175 g175 b175 0 219 2 1 218 -------- 1 218 3 2 217 -------- 2 217 4 3 216 -------- 3 216 5 4 215 -------- 4 215 6 5 214 -------- 5 214 7 6 213 -------- 6 213 8 7 212 -------- 7 212 || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | 213 212 7 -------- 212 7 214 213 6 -------- 213 6 215 214 5 -------- 214 5 216 215 4 -------- 215 4 217 216 3 -------- 216 3 218 217 2 -------- 217 2 219 218 1 -------- 218 1 220 219 0 -------- 219 0 mx=' 0 ' -------- mx=' 1 ' -------- 175 175 174 1 0 ca 0 1 174 rgb=0 rgb=1 rgb=0 rgb=1 ra sa source out rgb=0 rgb=1 rgb=0 rgb=1 rgb order pixel 1 pixel 2 pixel 175 pixel 176 note ra = row address, ca = column address sa = scan address mx = mirror x-axis (column address direction paramet er), d6 parameter of madctl command my = mirror y-axis (row address direction parameter) , d7 parameter of madctl command mx =scan direction parameter, d4 parameter of madctl c ommand rgb = red, green and blue pixel position change, d3 parameter of madctl command
ST7773 ver. 2.0 2008-07-07 45 9.9.3 normal display on or partial mode on, vertica l scroll off in this mode, contents of the frame memory within a n area where column pointer is 00h to afh and page p ointer is 00h to dbh is displayed. to display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0). 1). example for normal display on (mx=my=ml=0 ,smx= smy=0) 2). example for partial display on ( psl[7:0]=04h,pel[7:0]=d7h , mx=mv=ml=0 ,smx=smy=0) 00h 01h ---- ---- a6h a7h ---- afh 00h 00 01 0y 0z 1 01h 10 11 1y 1z 2 02h 20 21 2y 2z 3 | 30 31 3y 3z | | 40 41 4y 4z | | 50 51 5y 5z | | 60 6z | | | | | | | | u0 u1 uy uz | | v0 v1 vx vy vz | | w0 w1 w2 wx wy wz | | x0 x1 x2 xx xy xz 218 dah y0 y1 y2 y3 yw yx yy yz 219 dbh z0 z1 z2 z3 zw zx zy zz 220 176 x 220 x18bit fram e ram 176 columns 176 columns 220 lines scan order non-display area =4 lines display area =212 lines non-display area =4 lines 00 01 02 03 0w 0x 0y 0z g1 10 11 12 13 1w 1x 1y 1z g2 20 21 22 2x 2y 2z g3 30 31 32 3x 3y 3z | 40 41 42 4x 4y 4z | 50 51 5y 5z | 60 6z | || | | s0 sz | u0 u1 uy uz | v0 v1 v2 vx vy vz | w0 w1 w2 wx wy wz | x0 x1 x2 xx xy xz g218 y0 y1 y2 y3 yw yx yy yz g219 z0 z1 z2 z3 zw zx zy zz g220 176rgb x 220 lcd panel 00h 00 01 0y 0z g1 01h 10 11 1y 1z g2 02h 20 21 2y 2z g3 | 30 31 3y 3z | | 40 41 4y 4z | | 50 51 5y 5z | | 60 6z | | | | | | | | | | | | | | x0 x1 x2 xx xy xz g218 dah y0 y1 y2 y3 yw yx yy yz g219 dbh z0 z1 z2 z3 zw zx zy zz g220 176 x 220 x18bit lcd panel 176 columns 00h 01h ---- ---- a6h a7h ---- afh 00h 00 01 0y 0z 1 01h 10 11 1y 1z 2 02h 20 21 2y 2z 3 | 30 31 3y 3z | | 40 41 4y 4z | | 50 51 5y 5z | | 60 6z | | | | | | | | | | | | | | x0 x1 x2 xx xy xz 218 dah y0 y1 y2 y3 yw yx yy yz 219 dbh z0 z1 z2 z3 zw zx zy zz 220 176 x 220 x18bit frame ram 176 columns 220 lines display area =220 lines scan order
ST7773 ver. 2.0 2008-07-07 46 9.9.4 vertical scroll mode there is vertical scrolling, which are determined b y the commands vertical scrolling definition (33h) and vertical scrolling start address (37h). fig. 9.9.2 difference between scrolling and origina l when vertical scrolling definition parameters (tfa+vsa+bfa) =220. in this case, scrolling is applied as shown b elow. 1). example for tfa =3, vsa=215, bfa=2, ssa=4, ml=0: scrollin g 00h 01h ---- ---- ---- ---- ---- aeh afh 00h 00 01 02 03 0w 0x 0y 0z 1 01h 10 11 12 13 1w 1x 1y 1z 2 02h 20 21 22 2x 2y 2z 3 | 30 31 32 3x 3y 3z | | 40 41 42 4x 4y 4z | | 50 51 5y 5z | | 60 6z | | | | | | | | | | s0 sz | | u0 u1 uy uz | | v0 v1 v2 vx vy vz | | w0 w1 w2 wx wy wz | d9h x0 x1 x2 xx xy xz 218 dah y0 y1 y2 y3 yw yx yy yz 219 dbh z0 z1 z2 z3 zw zx zy zz 220 176 x 220 x18 bit fram e ram 176 columns 176 columns 220 lines scan order tfa vsa bfa 00 01 02 03 0w 0x 0y 0z g1 10 11 12 13 1w 1x 1y 1z g2 20 21 22 2x 2y 2z g3 40 41 42 4x 4y 4z | 50 51 5y 5z | 60 6z | || | | s0 sz | u0 u1 uy uz | v 0 v 1 v 2 v x v y v z | w 0 w 1 w 2 w x w y w z | x0 x 1 x2 x x x y xz | 30 31 32 3x 3y 3z g218 y0 y 1 y2 y 3 y w y x y y yz g219 z0 z 1 z2 z 3 z w z x z y zz g220 176r g b x 220 176r g b x 220 176r g b x 220 176r g b x 220 lc d panel lc d panel lc d panel lc d panel ssa
ST7773 ver. 2.0 2008-07-07 47 2). example for tfa =3, vsa=215, bfa=2, ssa=215, ml=1: scroll ing: tfa and bft are exchanged 00h 01h ---- ---- ---- ---- ---- aeh afh 00h 00 01 02 03 0w 0x 0y 0z 220 01h 10 11 12 13 1w 1x 1y 1z 219 02h 20 21 22 2x 2y 2z 218 | 30 31 32 3x 3y 3z | | 40 41 42 4x 4y 4z | | 50 51 5y 5z | | 60 6z | | | | | | | | | | s0 sz | | u0 u1 uy uz | | v0 v1 v2 vx vy vz | | w0 w1 w2 wx wy wz | d9h x0 x1 x2 xx xy xz 3 dah y0 y1 y2 y3 yw yx yy yz 2 dbh z0 z1 z2 z3 zw zx zy zz 1 176 x 220 x18 bit fram e ram 176 columns 176 columns 220 lines scan order bfa vsa tfa ssa 00 01 02 03 0w 0x 0y 0z g1 10 11 12 13 1w 1x 1y 1z g2 60 61 62 6x 6y 6z g3 70 71 72 7x 7y 7z | 80 81 82 8x 8y 8z | 90 9z | a0 az | || | | 20 21 22 2x 2y 2z | 30 31 32 3x 3y 3z | 40 41 42 4x 4y 4z | 50 51 5y 5z | x 0 x 1 x 2 x x x y x z g218 y 0 y 1 y 2 y 3 y w y x y y y z g219 z 0 z 1 z 2 z 3 z w z x z y z z g220 176r g b x 220 176r g b x 220 176r g b x 220 176r g b x 220 lcd panel lcd panel lcd panel lcd panel
ST7773 ver. 2.0 2008-07-07 48 9.9.5 vertical scroll example there are 2 types of vertical scrolling, which are determined by the commands vertical scrolling defin ition (33h) and vertical scrolling start address (37h). case 1: tfa + vsa + bfa 220 n/a. do not set tfa + vsa + bfa 220. in that case, unexpected picture will be shown . case 2: tfa + vsa + bfa=220 (scrolling) example1) when madctl parameter ml=0, tfa=0, vsa=220, bfa=0 and vscsad=80. example2) when madctl parameter ml=1, tfa=30, vsa=190 , bfa=0 and vscsad=80.
ST7773 ver. 2.0 2008-07-07 49 9.10 address counter the address counter sets the addresses of the displ ay data ram for writing and reading. data is written pixel-wise into the ram matrix of dr iver. the data for one pixel or two pixels is collect ed (rgb 6-6-6-bit), according to the data formats. as soon as this pixel -data information is complete the write access is activated on the ram. the locations of ram are addressed by the address po inters. the address ranges are x=0 to x=175 (afh) an d y=0 to y=219 (dbh). addresses outside these ranges are not allowed. before writing to the ram, a window must be defined that will be written. the window is programmable via the command registers xs, ys designating the start addre ss and xe, ye designating the end address. for example the whole display contents will be writ ten, the window is defined by the following values: xs=0 (0h) ys=0 (0h) and xe=175(afh), ye=219 (dbh). in vertical addressing mode (mv=1), the y-address in crements after each byte, after the last y-address (y=ye), y wraps around to ys and x increments to address the next co lumn. in horizontal addressing mode (v=0), the x-add ress increments after each byte, after the last x-addres s (x=xe), x wraps around to xs and y increments to ad dress the next row. after the every last address (x=xe and y=ye) the address pointers wrap around to address (x=xs and y= ys). for flexibility in handling a wide variety of displ ay architectures, the commands caset, raset and madctl (see section 10 command list), define flags mx and my, w hich allows mirroring of the x-address and y-addres s. all combinations of flags are allowed. section 9.12 show the available combinations of writing to the displ ay ram. when mx, my and mv will be changed the data bust be rewritten to the display ram. for each image condition, the controls for the colu mn and row counters apply as section 9.11 below: condition column counter row counter when ramwr/ramrd command is accepted return to start column (xs) return to start row (ys) complete pixel read / write action increment by 1 no change the column counter value is larger than end column (xe) return to start column (xs) increment by 1 the column counter value is larger than end column (xe) and the row counter value is larger than end row (ye) return to start column (xs) return to start row (ys)
ST7773 ver. 2.0 2008-07-07 50 9.11. memory data write/ read direction the data is written in the order illustrated above. the counter which dictates where in the physical m emory the data is to be written is controlled by memory data access control command, bits b5 (mv), b6 (mx), b7 (my) as described below. fig. 9.11.1 data streaming order physical row point madctl (36h) mv mx mv caset raset 0 0 0 direct to physical column pointer direct to physical row pointer 0 0 1 direct to physical column pointer direct to (219-phy sical row pointer) 0 1 0 direct to (175-physical column pointer) direct to phy sical row pointer 0 1 1 direct to (175-physical column pointer) direct to (2 19-physical row pointer) 1 0 0 direct to physical row pointer direct to physical col umn pointer 1 0 1 direct to (219-physical row pointer) direct to physic al column pointer 1 1 0 direct to physical row pointer direct to (175-physica l column pointer) 1 1 1 direct to (219-physical row pointer) direct to (175- physical column pointer) note: data is always written to the frame memory in the same order, regardless of the memory write dir ection set by madctl bits b7 (my), b6 (mx), b5 (mv). the write order for each pixel unit is one pixel unit represents 1 column and 1page counte r value on the frame memory.
ST7773 ver. 2.0 2008-07-07 51 9.11.2 frame data write direction according to the madctl parameters (mv, mx and my) madctl parameter display data direction mv mx my image in the host (mpu) image in the driver (ddram) normal 0 0 0 y-mirror 0 0 1 x-mirror 0 1 0 x-mirror y-mirror 0 1 1 x-y exchange 1 0 0 x-y exchange y-mirror 1 0 1 x-y exchange x-mirror 1 1 0 x-y exchange x-mirror y-mirror 1 1 1 h/w position (0,0) f h/w position (0,0) f h/w position (0,0) x-y address (0,0) x: raset y: caset b h/w position (0,0) x-y address (0,0) x: raset y: caset f h/w position (0,0) f b x-y address (0,0) x: caset y: raset b f h/w position (0,0) x-y address (0,0) x: caset y: raset h/w position (0,0) x-y address (0,0) x: caset y: raset b f b f h/w position (0,0) x-y address (0,0) x: caset y: raset b f b f b f b f b f b f b f b f b f b x-y address (0,0) x: raset y: caset b x-y address (0,0) x: raset y: caset
ST7773 ver. 2.0 2008-07-07 52 9.12 tearing effect output line the tearing effect output line supplies to the mpu a panel synchronization signal. this signal can be en abled or disabled by the tearing effect line off & on commands. the mod e of the tearing effect signal is defined by the pa rameter of the tearing effect line on command. the signal can be us ed by the mpu to synchronize frame memory writing wh en displaying video images. 9.12.1 tearing effect line modes mode 1 , the tearing effect output signal consists of v-blan king information only: tvdh= the lcd display is not updated from the frame memory tvdl= the lcd display is updated from the frame mem ory (except invisible line C see below) mode 2 , the tearing effect output signal consists of v-blan king and h-blanking information, there is one v-sync and 220 h-sync pulses per field. v-sync v-sync invisible line t vdh t vdl 1 st line 2 nd line 219 th line 220 th line vertical timing scale thdh= the lcd display is not updated from the frame memory thdl= the lcd display is updated from the frame mem ory (except invisible line C see above) note: during sleep in mode, the tearing output pin is active low.
ST7773 ver. 2.0 2008-07-07 53 9.12.2 tearing effect line timings the tearing effect signal is described below: table 9.12.1 ac characteristics of tearing effect sign al idle mode off (frame rate = 58.9 hz) symbol parameter min max unit description t vdl vertical timing low duration 13 - ms t vdh vertical timing high duration 1000 - s t hdl horizontal timing low duration 33 - s t hdh horizontal timing low duration 25 500 s note: the timings in table 9.3.1 apply when madctl ml =0 and ml=1 the signals rise and fall times (tf, tr) are stipu lated to be equal to or less than 15ns. the tearing effect output line is fed back to the mpu and should be used as shown below to avoid tearing effect:
ST7773 ver. 2.0 2008-07-07 54 9.12.3 example 1: mpu write is faster than panel re ad data write to frame memory is now synchronized to t he panel scan. it should be written during the vert ical sync pulse of the tearing effect output line. this ensures that da ta is always written ahead of the panel scan and ea ch panel frame refresh has a complete new image: b
ST7773 ver. 2.0 2008-07-07 55 9.12.4 example 2: mpu write is slower than panel re ad. the mpu to frame memory write begins just after panel read has commenced i.e. after one horizontal sync pulse of the tearing effect output line. this allows time for the image to download behind the panel read pointer an d finishing download during the subsequent frame before the rea d pointer catches the mpu to frame memory write po sition. b
ST7773 ver. 2.0 2008-07-07 56 9.13 preset values ST7773 will set preset values on our production line for each display module. any of these preset value s do not need customers sw support. 9.14 power on/off sequence the power on/off sequence is illustrated bleow:(vdd must be powered on then vddi) timing when the latter signal falls down to 90% of its typical value. tr pw-resx = tf pw-resx = min 120ms vdd vddi resx tr pw R 0 ns tf pw R 0ns min 10us system is reset immediately by low pulse of resx. about the hw reset setting, please refer to the sec . 9.18.3. e.g. when vdd comes later, this timing is defined a t the cross point of 90% of 2.8v, not 2.7v. timing when the latter signal rises up to 90% of it s typical value. e.g. when vdd comes later, this timing is defined a t the cross point of 90% of 2.8v, not 2.7v. 9.15.3 uncontrolled power off the uncontrolled power-off means a situation which removed a battery without the controlled power off sequence. it will neither damange the module or the host interface if uncontrolled power-off happened, the display wil l go blank and there will not be any visible effect s on the display (blank display) and remains blank until power on sequence powers it up.
ST7773 ver. 2.0 2008-07-07 57 9.16 power level definition 9.16.1 power level 6 level modes are defined they are in order of maxi mum power consumption to minimum power consumption: 1. normal mode on (full display), idle mode off, sl eep out. in this mode, the display is able to show maximum 2 62,144 colors. 2. partial mode on, idle mode off, sleep out. in this mode part of the display is used with maxim um 262,144 colors. 3. normal mode on (full display), idle mode on, slee p out. in this mode, the full display area is used but wit h 8 colors. 4. partial mode on, idle mode on, sleep out. in this mode, part of the display is used but with 8 colors. 5. sleep in mode in this mode, the dc: dc converter, internal oscill ator and panel driver circuit are stopped. only the mcu interface and memory works with vddi power supply. contents of the memory are safe. 6. power off mode in this mode, both vdd and vddi are removed. 9.16.2 power flow chart sleep out normal display mode on idle mode off sleep in normal display mode on idle mode off sleep out normal display mode on idle mode on sleep in normal display mode on idle mode on sleep out partial display mode on idle mode off sleep in partial display mode on idle mode off sleep out partial display mode on idle mode on sleep in partial display mode on idle mode on slp in slp in slp in slp in slp out slp out slp out slp out idm on idm off idm on idm off ptl on nor on ptl on nor on idm on idm off ptl on nor on ptl on nor on idm on idm off power on sequence hw reset sw reset normal display mode on = nor on partial display mode on = ptl on idle mode off = idm off idle mode on = idm on sleep out = slp out sleep in = slp in
ST7773 ver. 2.0 2008-07-07 58 9.17 reset table item after power on after hardware reset after software reset frame memory random no change no change sleep in/out in in in display on/off off off off display mode (normal/partial) normal normal normal display inversion on/off off off off display idle mode on/off off off off column: start address (xs) 0000h 0000h 0000h column: end address (xe) 00afh 00afh 00afh (175d) (when mv=0) 00dbh (219d) (when mv=1) row: start address (ys) 0000h 0000h 0000h row: end address (ye) 00dbh 00dbh 00dbh (219d) (when mv=0) 00afh (175d) (when mv=1) gamma setting gc0 gc0 gc0 rgb for 256, 4k and 65k color mode see section 9.19 see section 9.19 no change partial: start address (psl) 0000h 0000h 0000h partial: end address (pel) 00dbh 00dbh 00dbh scroll: vertical scrolling off off off scroll: top fixed area (tfa) 0000h 0000h 0000h scroll: scroll area (vsa) 00dch 00dch 00dch scroll: bottom fixed area (bfa) 0000h 0000h 0000h scroll start address (ssa) 0000h 0000h 0000h tearing: on/off off off off tearing effect mode *3) 0 (mode1) 0 (mode1) 0 (mode1 ) memory data access control (my/mx/mv/ml/rgb) 0/0/0/0/0 0/0/0/0/0 no change interface pixel color format 6 (18-bit/pixel) 6 (18-bi t/pixel) no change rddpm 08h 08h 08h rddmadctl 00h 00h no change rddcolmod 6 (18-bit/pixel) 6 (18-bit/pixel) no change rddim 00h 00h 00h rddsm 00h 00h 00h rddsdr 00h 00h 00h id1 29h 29h 29h id2 - - - note1. te mode 1 means tearing effect output line con sists of v-blanking information only. 9.18.1 module input/output pins 9.18.1.1 output or bi-directional (i/o) pins output or bi-directional pins after power on after hardware reset after software reset te low low low d17 to d0 (output driver) high-z (inactive) high-z (inactive) high-z (inactive) note: there will be no output from d7-d0 during powe r on/off sequence, hardware reset and software rese t. 9.18.1.2 input pins input pins during power on process after power on after hardware reset after software reset during power off process resx see 9.15 input valid input valid input valid see 9 .15 csx input invalid input valid input valid input vali d input invalid d/cx input invalid input valid input valid input va lid input invalid wrx input invalid input valid input valid input val id input invalid rdx input invalid input valid input valid input val id input invalid d17 to d0 input invalid input valid input valid inp ut valid input invalid p/sx input invalid input valid input valid input vali d input invalid
ST7773 ver. 2.0 2008-07-07 59 9.18.2 reset timing vss=0v, vddi=1.6 to 3.3v, vdd=2.7 to 3.3v, ta = 25 ) symbol parameter related pins min typ max note unit t resw *1) reset low pulse width resx 10 - - - us t rest reset complete time - 120 - - ms note 1 spike due to an electrostatic discharge on r esx line does not cause irregular system reset accordi ng to the table below. note 2. during reset complete time, id2 and vcomof v alue in eeprom will be latched to internal register du ring this period.this loading is done every time when there i s h/w reset complete time (trest) within 5ms after a rising edge of resx. note 3. spike rejection also applies during a valid reset pulse as shown below: resx pulse action shorter than 5us reset rejected longer than 10us reset between 5us and 10us reset starts (it depends on vol tage and temperature condition.) "reset" is accepted 10us 10us
ST7773 ver. 2.0 2008-07-07 60 9.19 external light source the operation of the module can meet customers envi ronmental reliability requirements. 9.20 oscillator the chip has on-chip oscillator that does not requi re external components. this oscillator output sign al is used for system clock generation for internal display operation. 9.21 system clock generator the timing generator produces the various signals t o driver the internal circuitty. internal chip oper ation is not affected by operations on the data bus. 9.22 instruction decoder and register the instruction decoder indentifies command words a rriving at the interface and routes the following d ata bytes to their destination. the command set can be found in comma nd section. 9.23 source driver the source driver block includes 176x3 source outpu ts (s1 to s528), which should be connected directly to the tft-lcd. the source output signals are generated in the data processing block after the data is read out of the ram and latched, which represent the simulatance selected rows. 9.24 gate driver the gate driver block includes 220 channel gate out put (g0 to g219) which should be connected directly to the tft-lcd. 5 6 7 8 9 10 11 12 1 2 3 4 s1 ? s528 g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 vgh vgl
ST7773 ver. 2.0 2008-07-07 61 10. command 10.1 system function command list and description table 10.1.1 system function command list (1) instruction refer d/cx wrx rdx d17- 8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function nop 10.1.1 0 1 - 0 0 0 0 0 0 0 0 (00h) no operation swreset 10.1.2 0 1 - 0 0 0 0 0 0 0 1 (01h) software reset 0 1 - 0 0 0 0 0 1 0 0 (04h) read display id 1 1 - - - - - - - - - dummy read 1 1 - id17 id16 id15 id14 id13 id12 id11 id10 id1 read rddid 10.1.3 1 1 - 1 id26 id25 id24 id23 id22 id21 id20 id2 read 0 1 - 0 0 0 0 1 0 0 1 (09h) read display status 1 1 - - - - - - - - - dummy read 1 1 - bston my mx mv ml rgb mh st24 - 1 1 - st23 ifpf2 ifpf1 ifpf0 idmon ptlon slout noron - 1 1 - vsson st14 invon st21 st11 dison teon gcs2 - rddst 10.1.4 1 1 - gcs1 gcs0 telon hson vson pckon deon st0 - 0 1 - 0 0 0 0 1 0 1 0 (0ah) read display power mode 1 1 - - - - - - - - - dummy read rddpm 10.1.5 1 1 - bston idmonptlon slpout noron dison d1 d0 - 0 1 - 0 0 0 0 1 0 1 1 (0bh read display madctl 1 1 - - - - - - - - - dummy read rdd madctl 10.1.6 1 1 - my mx mv ml rgb mh d1 d0 - 0 1 - 0 0 0 0 1 1 0 0 (0ch) read display pixel format 1 1 - - - - - - - - - dummy read rdd colmod 10.1.7 1 1 - d7 d6 d5 d4 d3 ifpf2 ifpf1 ifpf0 - 0 1 - 0 0 0 0 1 1 0 1 (0dh) read display image mode 1 1 - - - - - - - - - dummy read rddim 10.1.8 1 1 - vsson d6 invon d4 d3 gcs2 gcs1 gcs0 - 0 1 - 0 0 0 0 1 1 1 0 (0eh) read display signal mode 1 1 - - - - - - - - - dummy read rddsm 10.1.9 1 1 - teon telon hson vson pckon deon d1 d0 - -: dont care
ST7773 ver. 2.0 2008-07-07 62 table 10.1.2 system function command list (2) instruction refer d/cx wrx rdx d17- 8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function slpin 10.1.11 0 1 - 0 0 0 1 0 0 0 0 (10h) sleep in & booster off slpout 1 0.1.12 0 1 - 0 0 0 1 0 0 0 1 (11h) sleep out & booster on ptlon 10.1.13 0 1 - 0 0 0 1 0 0 1 0 (12h) partial mode on noron 10.1.14 0 1 - 0 0 0 1 0 0 1 1 (13h) partial mode off (normal) invoff 10.1.15 0 1 - 0 0 1 0 0 0 0 0 (20h) display inversion off (normal) invon 10.1.16 0 1 - 0 0 1 0 0 0 0 1 (21h) display inversion on 0 1 - 0 0 1 0 0 1 1 0 (26h) gamma curve select gamset 10.1.17 1 1 - - - - - gc3 gc2 gc1 gc0 - dispoff 10.1.18 0 1 - 0 0 1 0 1 0 0 0 (28h) display off dispon 10.1.19 0 1 - 0 0 1 0 1 0 0 1 (29h) display on 0 1 - 0 0 1 0 1 0 1 0 (2ah) column address set 1 1 - xs15 xs14 xs13 xs12 xs 11 xs10 xs9 xs8 x address start: 0 s x Q Q 1 1 - xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 1 1 - xe15 xe14 xe13 xe12 xe11 xe10 xe9 xe8 x address end: xs xe x Q Q caset 10.1.20 1 1 - xe7 xe6 xe5 xe4 xe3 xe2 xe1 xe0 0 1 - 0 0 1 0 1 0 1 1 (2bh) row address set 1 1 - ys15 ys14 ys13 ys12 ys11 ys10 ys9 ys8 y address start: 0 Q ys y Q 1 1 - ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 1 1 - ye15 ye14 ye13 ye12 ye11 ye10 ye9 ye8 y address end: ys ye y Q Q raset 10.1.21 1 1 - ye7 ye6 ye5 ye4 ye3 ye2 ye1 ye0 0 1 - 0 0 1 0 1 1 0 0 (2ch) memory write ramwr 10.1.22 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 write data 0 1 - 0 0 1 0 1 1 1 0 (2eh) memory read 1 1 - - - - - - - - - dummy read ramrd 10.1.23 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 read data -: dont care
ST7773 ver. 2.0 2008-07-07 63 table 10.1.3 system function command list (3) instruction refer d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function 0 1 - 0 0 1 1 0 0 0 0 (30h) partial start/end address set 1 1 - psl15 psl14 psl13 psl12 psl11 psl10 psl9 psl8 1 1 - psl7 psl6 psl5 psl4 psl3 psl2 psl1 psl0 partial start address (0,1,2, ..p) 1 1 - pel15 pel14 pel13 pel12 pel11 pel10 pel9 pel8 ptlar 10.1.24 1 1 - pel7 pel6 pel5 pel4 pel3 pel2 pel1 pel0 partial end address (0,1,2, .., p) 0 1 - 0 0 1 1 0 0 1 1 (33h) scroll area set 1 1 - tfa15 tfa14 tfa13 tfa12 tfa11 tfa10 tfa9 tfa8 1 1 - tfa7 tfa6 tfa5 tfa4 tfa3 tfa2 tfa1 tfa0 top fixed area (0,1,2, .., s) 1 1 - vsa15vsa14vsa13vsa12 vsa11vsa10 vsa9 vsa8 1 1 - vsa7 vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 vertical scroll area (0,1,2, .., s) 1 1 - bfa15 bfa14 bfa13 bfa12 bfa11 bfa10 bfa9 bfa8 scrlar 10.1.25 1 1 - bfa7 bfa6 bfa5 bfa4 bfa3 bfa2 bfa1 bfa0 bottom fixed area (0,1,2, .., s) teoff 10.1.26 0 1 - 0 0 1 1 0 1 0 0 (34h) tearing effect line off 0 1 - 0 0 1 1 0 1 0 1 (35h) tearing effect mode set & on teon 10.1.27 1 1 - - - - - - - - m m=0: mode1, m=1: mode2 0 1 - 0 0 1 1 0 1 1 0 (36h) memory data access control madctl 10.1.28 1 1 - my mx mv ml rgb mh 0 0 - 0 1 - 0 0 1 1 0 1 1 1 (37h) scroll start address of ram 1 1 - - - - - - - - ssa8 ssa = 0, 1, 2, , 175 vscsad 10.1.29 1 1 - ssa7 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssa0 idmoff 10.1.30 0 1 - 0 0 1 1 1 0 0 0 (38h) idle mode off idmon 10.1.31 0 1 - 0 0 1 1 1 0 0 1 (39h) idle mode on 0 1 - 0 0 1 1 1 0 1 0 (3ah) interface pixel format colmod 10.1.32 1 1 - - - - - 0 ifpf2 ifpf1ifpf0 interface format 0 1 - 1 1 0 1 1 0 1 0 (dah) read id1 1 1 - - - - - - - - - dummy read rdid1 10.1.33 1 1 - id17 id16 id15 id14 id13 id12 id11 id10 read parameter 0 1 - 1 1 0 1 1 0 1 1 (dbh) read id2 1 1 - - - - - - - - - dummy read rdid2 10.1.34 1 1 - id27 id26 id25 id24 id23 id22 id21 id20 read parameter 0 1 - 1 1 0 1 1 1 0 0 (dch) read id3 1 1 - - - - - - - - - dummy read rdid3 10.1.35 1 1 - id37 id36 id35 id34 id33 id32 id31 id30 read parameter -: dont care note 1: after the h/w reset by resx pin or s/w reset by swreset command, each internal register becomes default state (refer reset table section) note 2: undefined commands are treated as nop (00 h) command. note 3: de to ff are for factory use of driver supplier. note 4: commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ml parameter only), 37h, 38h and 39h are updated during v-sync when module is in sleep out mode to avoid abnormal visual effects. during sleep in mode, these commands are updated immediately. read status (09h), read display power mode (0ah), read display madctl (0bh), read display pixel format (0ch), read display image mode (0dh), read display signal mode (0eh) of these commands are updated immediately both in sleep in mode and sleep out mode.
ST7773 ver. 2.0 2008-07-07 64 10.2 panel function command list and description table 10.2.1 panel function command list (1) instruction refer d/cx wrx rdx d23-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function 0 1 - 1 0 1 1 0 0 0 1 (b1h) in normal mode (full colors) - rtna[7:0] - 0 0 1 1 1 0 1 1 0 0 0 fpa[4:0] - 0 0 0 0 0 1 0 0 - 0 0 0 bpa[4:0] - 0 0 0 0 0 0 1 1 rtna_vsync[7:0] frmctr1 10.2.2 1 1 0 0 1 1 1 0 0 0 rtna_vsync setting for vsync mode 0 1 - 1 0 1 1 0 0 1 0 (b2h) in idle mode (8 colors) rtnb[7:0] 0 0 1 1 1 0 1 1 0 0 0 fpb[4:0] 0 0 0 0 0 1 0 0 bpb[4:0] frmctr2 10.2.3 1 1 0 0 0 1 1 0 1 - 1 0 1 1 0 0 1 0 (b3h) in partial mode (full colors) rtnc[7:0] 0 0 1 1 1 0 1 1 0 0 0 fpc[4:0] 0 0 0 0 0 1 0 0 bpc[4:0] frmctr3 10.2.4 1 1 0 0 0 1 1 0 1 - 1 0 1 1 0 1 0 0 (b4h) display inversion control - 0 0 0 0 0 nla nlb nlc invctr 10.2.5 1 1 - 0 0 0 0 0 0 0 0 nla:,nlb,nlc set inversion 0 1 - 1 0 1 1 0 1 1 0 (b6h) display function setting - 0 0 no1 no0 sdt1 sdt0 eq1 eq0 - 0 0 0 1 0 1 0 1 0 0 0 0 ptg1 ptg0 pt1 pt0 disset5 10.2.7 1 1 0 0 0 0 0 0 0 0 no: the amount of non-overlap sdt: set amount of source delay pt: no display area source/ vcom/ gate output control eq: set eq period
ST7773 ver. 2.0 2008-07-07 65 table 10.2.2 panel function command list (2) instruction refer d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function 0 1 - 1 1 0 0 0 0 0 0 (c0h) power control setting - 0 0 0 vrh4 vrh3 vrh2 vrh1 vrh0 pwctr1 10.2.10 1 1 - 0 0 0 0 0 1 0 1 vrh: set the gvdd voltage 0 1 - 1 1 0 0 0 0 0 1 (c1h) power control setting - vgh3 vgh2 vgh1 vgh0 vgl3 vgl2 vgl1 vgl0 vgh: set vgh voltage vgl: set vgl voltage pwctr2 10.2.11 1 1 1 0 1 1 1 0 1 1 0 1 - 1 1 0 0 0 0 1 0 (c2h) in normal mode (full colors) - 0 0 0 0 0 apa2 apa1 apa0 pwctr3 10.2.12 1 1 - 0 0 0 0 0 1 0 0 ap: adjust the operational amplifier dc: adjust the booster circuit for idle mode 0 1 - 1 1 0 0 0 0 1 1 (c3h) in idle mode (8-colors) - 0 0 0 0 0 apb2 apb1 apb0 pwctr4 10.2.13 1 1 - 0 0 0 0 0 0 1 0 ap: adjust the operational amplifier dct: adjust the booster circuit for idle mode 0 1 - 1 1 0 0 0 1 0 0 (c4h) in partial mode + full colors - 0 0 0 0 0 apc2 apc1 apc0 pwctr5 10.2.14 1 1 - 0 0 0 0 0 1 0 0 ap: adjust the operational amplifier dct: adjust the booster circuit for idle mode 0 1 - 1 1 0 0 0 1 0 1 (c5h) vcom control 1 - 0 vmh6 vmh 5 vmh4 vmh3 vmh2 vmh1 vmh0 1 1 - 0 0 1 1 1 1 0 0 - 0 vml6 vml5 vml4 vml3 vml2 vml1 vml0 vmctr1 10.2.15 1 1 - 0 0 1 1 1 1 0 0 vmh: vcomh voltage control vml: vcoml voltage control 0 1 - 1 1 0 0 0 1 1 1 (c7h) vcom offset control - nvm* vmf6 vmf5 vmf4 vmf3 vmf2 vmf1 vmf0 vmofctr 10.2.16 1 1 - 0 0 1 1 1 1 0 0 0 1 - 1 1 0 0 1 0 0 1 (c9h) step124 setup - dual_en step_div_en 1 0 0 cp1_freq_sel[2:0] 1 0 1 0 0 1 0 0 - nw_mode 0 0 0 0 cp2_freq_sel[2:0] - 0 0 0 0 0 1 0 0 - 0 0 0 0 0 cp4_freq_sel[2:0] step ctr 10.2.17 1 - 0 0 0 0 0 1 0 0 adjust step1/2/4 booster frequency - 1 1 1 1 0 1 0 0 (f4h) - 0 1 0 1 rd_pulse_width[3:0] - 0 0 0 0 0 1 0 1 adjust read gram timing control function 0 1 - 1 1 1 1 1 0 0 0 (f8h) - 0 0 0 0 0 8-color 0 0 8-color detect function 8-color ctr 10.2.18 1 1 - 0 0 0 0 0 1 0 0 0 1 - 1 1 1 1 1 1 0 0 (fch) gate operational amplifier control - 0 0 1 1 1 sapa[2:0] - 0 0 1 1 1 1 0 0 - 0 1 1 1 1 sapb[2:0] - 0 1 1 1 1 1 0 0 - 0 0 0 0 0 sapc[2:0] pwctr6 10.2.19 1 1 - 0 0 0 0 0 1 0 0 sapa.: normal mode sapb : idle mode sapc : partial mode -: dont care
ST7773 ver. 2.0 2008-07-07 66 table 10.2.3 panel function command list (3) instruction refer d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function 0 1 - 1 1 0 1 0 0 0 1 (d1h) lcm version code - 0 id26 id25 id24 id23 id22 id21 id20 wrid2 10.2.20 1 1 - 1 0 0 0 0 0 0 0 write id2 value to nv memory set the lcm version code at id2 0 1 - 1 1 0 1 1 1 1 0 (deh) mtp read command nvctr2 10.2.23 1 1 - 1 0 1 0 1 0 1 0 75 0 1 - 1 1 0 1 1 1 1 1 (dfh) mtp write command 1 1 - 0 1 0 1 0 1 0 1 55 1 1 - 1 1 1 1 0 0 0 0 f0 nvctr3 10.2.24 1 1 - 0 1 0 1 1 0 1 0 5a -: dont care note 1: the d1h to d3h registers are fixed for about id code setting. note 2: the deh and dfh registers are used for nv memory function controller. (ex: write, clear, etc.)
ST7773 ver. 2.0 2008-07-07 67 table 10.2.4 panel function command list (4) instruction refer d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function 0 1 - 1 1 1 0 0 0 0 0 (e0h) set gamma correction - --- --- vrf0p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- vos0p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk0p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk1p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk2p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk3p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk4p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk5p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk6p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk7p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk8p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk9p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- selv0p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- selv1p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- selv62p[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- selv63p[5:0] gamctrp1 1 1 - 0 0 0 0 0 0 0 0 postiive polarity 0 1 - 1 1 1 0 0 0 0 1 (e1h) set gamma correction - --- --- vrf0n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- vos0n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk0n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk1n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk2n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk3n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk4n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk5n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk6n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk7n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk8n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- pk9n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- selv0n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- selv1n[5:0] gamctrn1 1 1 - 0 0 0 0 0 0 0 0 negative polarity
ST7773 ver. 2.0 2008-07-07 68 - --- --- selv62n[5:0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- selv63n[5:0] gamctrn1 1 1 - 0 0 0 0 0 0 0 0 negative polariy -: dont care note 1: e0-e1 registers are fixed for about gamma adjusting.
ST7773 ver. 2.0 2008-07-07 69 10.1.1 nop (00h) 00h nop (no operation) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) nop 0 1 - 0 0 0 0 0 0 0 0 (00h) parameter no parameter - note: - dont care description -this command is empty command. 10.1.2 swreset (01h): software reset 01h swreset (software reset) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) swreset 0 1 - 0 0 0 0 0 0 0 1 (01h) parameter no parameter - note: - dont care description - when the software reset command is written, it causes a software reset. it resets the commands and parameters to their s/w reset default values and all source & gate outputs are set to vss (display off). -it will be necessary to wait 5msec before sending new command following software reset. -the display module loads all default values to the registers during 5msec. -if software reset is applied during sleep out mode, it will be necessary to wait 120msec before sending sleep out command. -software reset command cannot be sent during sleep out sequence. 10.1.3 rddid (04h): read display id 04h rddid (read display id) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddid 0 1 - 0 0 0 0 0 1 0 0 (04h) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 - id17 id16 id15 id14 id13 id12 id11 id10 3 rt parameter 1 1 - 1 id26 id25 id24 id23 id22 id21 id20 note: - dont care description -this read byte returns 24-bit display identification information. -the 1st parameter is dummy data -the 2nd parameter (id17 to id10): lcd modules manufacturer id. -the 3rd parameter (id27 to id20): lcd module/driver version id note: commands rdid1/2(dah, dbh) read data correspond to the parameters 2,3, of the command 04h, respectively. default default value status id1 id2 power on sequence - - s/w reset 29h 29h h/w reset 81h 81h
ST7773 ver. 2.0 2008-07-07 70 10.1.4 rddst (09h): read display status 09h rddst (read display status) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddst 0 1 - 0 0 0 0 1 0 0 1 (09h) 1st parameter 1 1 - - - - - - - - - - 2nd parameter 1 1 - bston my mx mv ml rgb mh st24 3rd parameter 1 1 - st23 ifpf2 ifpf1 ifpf0 idmon ptlon slout noron 4th parameter 1 1 - vsson st14 invon st12 st11 dison teon gcs2 5th parameter 1 1 gcs1 gcs0 telom hson vson pckon deon st0 note: - dont care description this command indicates the current status of the display as described in the table below: bit description value bston booster voltage status 1 =booster on, 0 =booster off my row address order (my) 1 =decrement, (bottom to top, when madctl (36h) d7=1) 0 =increment, (top to bottom, when madctl (36h) d7=0) mx column address order (mx) 1 =decrement, (right to left, when madctl (36h) d6=1) 0 =increment, (left to right, when madctl (36h) d6=1) mv row/column exchange (mv) 1 = row/column exchange, (when madctl (36h) d5=1) 0 = normal, (when madctl (36h) d5=0) ml scan address order (ml) 1 =decrement, (lcd refresh top to bottom, when madctl (36h) d4=1) 0=increment, (lcd refresh bottom to top, when madctl (36h) d4=0) rgb rgb/ bgr order (rgb) 1 =bgr, (when madctl (36h) d3=1) 0 =rgb, (when madctl (36h) d3=0) mh horizontal order 1 =decrement, (lcd refresh left to right, when madctl (36h) d2=1) 0 =increment, (lcd refresh right to left, when madctl (36h) d2=0) st24 for future use 0 st23 for future use 0 ifpf2 ifpf1 ifpf0 interface color pixel format definition 011 = 12-bit / pixel, 101 = 16-bit / pixel, 110 = 18-bit / pixel, others are no define idmon idle mode on/off 1 = on, 0 = off ptlon partial mode on/off 1 = on, 0 = off slpout sleep in/out 1 = out, 0 = in noron display normal mode on/off 1 = normal display, 0 = partial display vsson vertical scrolling status 1 = scroll on,0 = scroll off st14 horizontal scroll status 0 invon inversion status 1 = on, 0 = off st12 all pixels on (not used) 0 st11 all pixels off (not used) 0 dison display on/off 1 = on, 0 = off teon tearing effect line on/off 1 = on, 0 = off gcsel2 gcsel1 gcsel0 gamma curve selection 000 = gc0 001 = gc1 010 = gc2 011 = gc3 100 to 111 = not defined telom tearing effect line mode 0 = mode1, 1 = mode2 hson horizontal sync. (hs, rgb i/f) 1 = on, 0 = off vson vertical sync, (vs, rgb i/f) 1 = on, 0 = off pclkon pixel clock (pclk, rgb i/f) 1 = on, 0 = off deon data enable (de, rgb i/f) 1 = on, 0 = off st0 for future use 0 note: st0, st5, st9, st11-st15, st19, st23, st24 are set to 0, when rgb i/f. default status default value (st31 to st0) st[31-24] st[23-16] st[15-8] st[7-0] power on sequence 0000-0000 0110-0001 0000-0000 0000-0000 s/w reset 0xxx0xx00 0xxx-0001 0000-0000 0000-0000 h/w reset 0000-0000 0110-0001 0000-0000 0000-0000
ST7773 ver. 2.0 2008-07-07 71 10.1.5 rddpm (0ah): read display power mode 0ah rddpm (read display power mode) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddpm 0 1 - 0 0 0 0 1 0 1 0 (0ah) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 bston idmon ptlon slpout noron dison d1 d0 note: - dont care, can be set to vddi or dgnd level description this command indicates the current status of the display as described in the table below: bit description value bston booster voltage status 1 =booster on, 0 =booster off idmon idle mode on/off 1 = idle mode on, 0 = idle mode off ptlon partial mode on/off 1 = partial mode on, 0 = partial mode off slpon sleep in/out 1 = sleep out, 0 = sleep in noron display normal mode on/off 1 = normal display, 0 = partial display dison display on/off 1 = display on, 0 = display off d1 not used 0 d0 not used 0 default status default value (d7 to d0) power on sequence 0000_1000(08h) s/w reset 0000_1000(08h) h/w reset 0000_1000(08h) 10.1.6 rddmadctl (0bh): read display madctl 0bh rddmadctl (read display madctl) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddmadctl 0 1 - 0 0 0 0 1 0 1 1 (0bh) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 my mx mv ml rgb mh d1 d0 note: - dont care, can be set to vddi or dgnd level description this command indicates the current status of the display as described in the table below: bit description value mx row address order 1 = bottom to top (when madctl b7=1) 0 = top to bottom (when madctl b7=0) my column address order 1 = right to left (when madctl b6=1) 0 = left to right (when madctl b6=0) mv row/column order (mv) 1 = row/column exchange (mv=1) 0 = normal (mv=0) ml vertical refresh order 1 =lcd refresh bottom to top 0 =lcd refresh top to bottom rgb rgb/bgr order 1 =bgr, 0=rgb mh horizontal order 1 =lcd refresh right to left 0 =lcd refresh left to right d1 not used 0 d0 not used 0 default status default value (d7 to d0) power on sequence 0000_0000 (00h) s/w reset no change h/w reset 0000_0000 (00h)
ST7773 ver. 2.0 2008-07-07 72 10.1.7 rddcolmod (0ch): read display pixel format 0ch rddcolmod (read display pixel format) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddcolmod 0 1 - 0 0 0 0 1 1 0 0 (0ch) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 - vipf3 vipf2 vipf1 vipf0 d3 ifpf2 ifpf1 ifpf0 note: - dont care, can be set to vddi or dgnd level description this command indicates the current status of the display as described in the table below: ifpf[2:0] mcu interface color format 011 3 12-bit/pixel 101 5 16-bit/pixel 110 6 18-bit/pixel 111 7 no used others are no define and invalid vifpf[2:0] rgb interface color format 0101 5 16-bit/pixel (1-times data transfer) 0110 6 18-bit/pixel (1-times data transfer) 0111 7 no used 1110 14 18-bit/pixel (3-times data transfer) others are no define and invalid default status default value ifpf[2:0] vipf[3:0] power on sequence 0110 (18 bits/pixel) 0110 (18 bits/pixel) s/w reset no change no change h/w reset 0110 (18 bits/pixel) 0110 (18 bits/pixel) 10.1.8 rddim (0dh): read display image mode 0dh rddim (0dh): read display image mode inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddim 0 1 - 0 0 0 0 1 1 0 1 (0dh) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 - vsson d6 invon d4 d3 gcs2 gcs1 gcs0 note: - dont care, can be set to vddi or dgnd level description this command indicates the current status of the display as described in the table below: bit description value vsson vertical scrolling on/off 1 = vertical scrolling is on, 0 = vertical scrolling is off d6 horizontal scrolling on/off 0 (not used) invon inversion on/off 1 = inversion is on, 0 = inversion is off d4 all pixels on 0 (not used) d3 all pixels off 0 (not used) gcs2 gcs1 gcs0 gamma curve selection 000 = gc0, 001 = gc1, 010 = gc2, 011 = gc3, 100 to 111 = not defined default status default value(d7 to d0) power on sequence 0000_0000 (00h) s/w reset 0000_0000 (00h) h/w reset 0000_0000 (00h)
ST7773 ver. 2.0 2008-07-07 73 10.1.9 rddsm (0eh): read display signal mode 0eh rddsm (0eh): read display signal mode inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddsm 0 1 - 0 0 0 0 1 1 1 0 (0eh) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 - teon telom hson vson pckon deon d1 d0 note: - dont care, can be set to vddi or dgnd level description this command indicates the current status of the display as described in the table below: bit description value teon tearing effect line on/off 1 = on, 0 = off telom tearing effect line mode 1 = mode1, 0 = mode2 hson horizontal sync. (rgb i/f) on/off 1 = on, 0 = off vson vertical sync. (rgb i/f) on/off 1 = on, 0 = off pckon pixel clock (pclk, rgb i/f) on/off 1 = on, 0 = off deon data enable (de, rgb i/f) on/off 1 = on, 0 = off d1 not used 1 = on, 0 = off d0 not used 1 = on, 0 = off default status default value(d7~d0) power on sequence 0000_0000 (00h) s/w reset 0000_0000 (00h) h/w reset 0000_0000 (00h)
ST7773 ver. 2.0 2008-07-07 74 10.1.10 slpin (10h): sleep in 10h slpin (sleep in) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) slpin 0 1 - 0 0 0 1 0 0 0 0 (10h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd level description -this command causes the lcd module to enter the minimum power consumption mode. -in this mode the dc/dc converter is stopped, internal display oscillator is sto pped, and panel scanning is stopped. restriction - this command has no effect when module is already in sleep in mode. sleep in mode can only be exit by the sleep out command (11h). -it will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. -it will be necessary to wait 120msec after sending sleep out command (when in sleep in mode) before sleep in command can be sent. default status default value power on sequence sleep in mode s/w reset sleep in mode h/w reset sleep in mode sl ee p in v d di 1.6 v - 3. 6 v v dd gate output source output 0v blanking display (over 1frame display) * v com output 0v 2. 7 v - 3. 5 v stop 0v internal counter stop internal oscillator st o p dc c ha rg e in c a p a c i t o rs disc h arge 0 v o r vdd v gh 0v or vdd vgl 0v avdd 0v or vdd ic internal reset 0v * note: complete 1 frame display (ex: continue 2-falling edges of vs)
ST7773 ver. 2.0 2008-07-07 75 10.1.11 slpout (11h): sleep out 11h slpout (sleep out) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) slpout 0 1 - 0 0 0 1 0 0 0 1 (11h) 1st parameter no parameter - note: - dont care, can be set to vddi or dgnd level description -this command turns off sleep mode. -in this mode the dc/dc converter is enabled, internal display oscillator is star ted, and panel scanning is started. restriction - this command has no effect when module is already in sleep out mode. sleep out mode can only be exit by the sleep in command (10h). -it will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. - driver loads all default values of extended and test command to the registers during this 5msec and there cannot b e any abnormal visual effect on the display image if those default and register values are same when this load is done and when the driver is already sleep out mode. -driver is doing self-diagnostic functions during this 5msec . see also section 9.20. -it will be necessary to wait 120msec after sending sleep in command (when in sleep out mode) before sleep out command can be sent default status default value power on sequence sleep in mode s/w reset sleep in mode h/w reset sleep in mode s l ee p o ut v ddi 1.6 v - 3. 6 v vdd internal oscillator stop start avdd 0v or vdd vgl 0v vgh 0v or vdd internal counter stop start ic internal reset 0v 2. 7 v - 3. 5 v g a t e output source output v com output s t op 0v 0v s t op 0v 0v me m ory con t en ts me m ory co n t e n ts b la n k ing di s p la y ( o v e r 1 f r a m e di s p lay ) * if d i s pon 2 9h i s s et * no t e : c o mp le t e 1 fr a me d is pl a y ( ex : c o nt i nue 2 - f a l l ing e dg e s o f v s)
ST7773 ver. 2.0 2008-07-07 76 10.1.12 ptlon (12h): partial display mode on 12h ptlon (12h): partial display mode on inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ptlon 0 1 - 0 0 0 1 0 0 1 0 (12h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd level description - this command turns on partial mode. the partial mode window is described by the partial area command (30h) -to leave partial mode, the normal display mode on command (13h) should be written. default status default value power on sequence normal mode on s/w reset normal mode on h/w reset normal mode on 10.1.13 noron (13h): normal display mode on 13h noron (normal display mode on) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) noron 0 1 - 0 0 0 1 0 0 1 1 (13h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd level description -this command returns the display to normal mode. -normal display mode on means partial mode off , scroll mode off . -exit from noron by the partial mode on command (12h) default status default value power on sequence normal mode on s/w reset normal mode on h/w reset normal mode on 10 .1.14 invoff (20h): display inversion off 20h ivnoff (normal display mode off) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) invoff 0 1 - 0 0 1 0 0 0 0 0 (20h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd level description -this command is used to recover from display inversion mode. default status default value power on sequence display inversion off s/w reset display inversion off h/w reset display inversion off t op - le f t (0,0) (e x amp le ) me m o ry d is pl ay
ST7773 ver. 2.0 2008-07-07 77 10.1.15 invon (21h): display inversion on 21h ivnoff (display inversion on) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) invon 0 1 - 0 0 1 0 0 0 0 1 (21h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd level description -this command is used to enter into display inversion mode -to exit from display inversion on, the display inversion off command (20h) should be written. default status default value power on sequence display inversion off s/w reset display inversion off h/w reset display inversion off 10.1.16 gamset (26h): gamma set 26h gamset (gamma set) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) gamset 0 1 - 0 0 1 0 0 1 1 0 (26h) 1 st parameter 1 1 - gc7 gc6 gc5 gc4 gc3 gc2 gc1 gc0 note: - dont care, can be set to vddi or dgnd level description -this command is used to select the desired gamma curve for the current display. a maximum of 4 curves can be selected. the curves are defined in section 9.17 the curve is sel ected by setting the appropriate bit in the parameter as described in the table. gc [7:0] parameter curve selected gs=1 01h gc0 gamma curve 1 (g2.2) 02h gc1 gamma curve 2 (g1.8) 04h gc2 gamma curve 3 (g2.5) 08h gc3 gamma curve 4 (g1.0) note: all other values are undefined. default status default value power on sequence 01h s/w reset 01h h/w reset 01h t op - le f t (0,0) (e x a mp le ) m e m o ry d is pl ay
ST7773 ver. 2.0 2008-07-07 78 10.1.17 dispoff (28h): display off 28h dispoff (display off) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) dispoff 0 1 - 0 0 1 0 1 0 0 0 (28h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd level description -this command is used to enter into display off mode. in this mode, the output from frame memory is disables and blank page inserted. -exit from this command by display on (29h) default status default value power on sequence display off s/w reset display off h/w reset display off t op - le f t (0,0) (e x amp l e) me m o r y d i s p lay v d di d is pl a y o ff 1.6 v - 3. 6 v v dd gate output source output 0v blanking display (over 1 frame display) * 2. 7 v - 3. 5 v s t o p vcom output 0v 0v internal counter stop i n t e rn a l o s c i l la t o r v g h v gl a v d d ic int e rn a l r e s e t * n o t e : c o mpl e t e 1 f r a m e di s p la y ( ex : c o ntin u e 2 - f al l i ng e dg e s o f v s)
ST7773 ver. 2.0 2008-07-07 79 10.1.18 dispon (29h): display on 29h dispon (display on) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) dispon 0 1 - 0 0 1 0 1 0 0 1 (29h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd level description -this command is used to recover from display off mode. output from the frame memory is enabled. default status default value power on sequence display off s/w reset display off h/w reset display off t op - le f t (0,0) (e x amp l e) me m o r y d i s pl ay v d di vdd gate output s o ur c e outp u t di s p la y on blanking display (over 1 frame display) * stop 0v 1.6 v - 3. 6 v 2.7v-3.5v m e m or y co n te n ts vcom output 0v memory contents internal counter stop start int e rn a l o s ci l l a t o r vgh vgl a v dd ic int e r na l r e s e t * no t e : c o m p l e te 1 fr a me d i s pl a y ( ex : c o ntinu e 2 - f a l l ing e dg e s o f v s )
ST7773 ver. 2.0 2008-07-07 80 10.1.19 caset (2ah): column address set 2ah caset(colume address set)_ inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) gamset 0 1 - 0 0 1 0 0 1 1 0 (2ah) 1 st parameter 1 1 - xs15 xs14 xs13 xs12 xs11 xs10 xs9 xs8 2 nd parameter 1 1 xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 3 rd parameter 1 1 xe15 xe14 xe13 xe12 xe11 xe10 xe9 xe8 4 th parameter 1 1 xe7 xe6 xe5 xe4 xe3 xe2 xe1 xe0 note: - dont care, can be set to vddi or dgnd level description -the value of xs [15:0] and xe [15:0] are referred when ramwr command comes. -each value represents one column line in the frame memory. estriction xs [15:0] always must be equal to or less than xe [15:0] when xs [15:0] or xe [15:0] is greater than maximum address like below, data of out of range will be ignored. (parameter range: 0 Q xs [15:0] Q xe [15:0] Q 175 (00afh)): mv=0 (parameter range: 0 Q xs [15:0] Q xe [15:0] Q 219 (00dbh)): mv=1 default default value status xs [15:0] xe [15:0] (mv= 0 ) xe [15:0] (mv= 1 ) power on sequence 00afh (175) s/w reset 00afh (175) 00dbh (219) h/w reset 0000h 00afh (175) ( e x a m p l e ) xs[15:0] xe[15:0]
ST7773 ver. 2.0 2008-07-07 81 10.1.20 raset (2bh): row address set 2bh raset (row address set) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) raset (2bh) 0 1 - 0 0 1 0 1 0 1 1 (2bh) 1st parameter 1 1 - ys15 ys14 ys13 ys12 ys11 ys10 ys9 ys8 2nd parameter 1 1 - ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 3rd parameter 1 1 - ye15 ye14 ye13 ye12 ye11 ye10 ye9 ye8 4th parameter 1 1 - ye7 ye6 ye5 ye4 ye3 ye2 ye1 ye0 note: - dont care, can be set to vddi or dgnd level description the value of ys [15:0] and ye [15:0] are referred when ramwr command comes. each value represents one column line in the frame memory. restriction ys [15:0] always must be equal to or less than ye [15:0] when ys [15:0] or ye [15:0] are greater than maximum row address like below, data of out of range will be ignored. (parameter range: 0 Q ys [15:0] Q ye [15:0] Q 219 (00dbh)): mv=0 (parameter range: 0 Q ys [15:0] Q ye [15:0] Q 175 (009fh)) : mv=1 default default value status ys [15:0] ye [15:0] (mv= 0 ) ye [15:0] (mv= 1 ) power on sequence 0000h 00dbh (219) s/w reset 0000h 00dbh (219) 00afh (175) h/w reset 0000h 00dbh (219) y s[15:0] y e[1 5 : 0] example
ST7773 ver. 2.0 2008-07-07 82 10.1.21 ramwr (2ch): memory write 2ch ramwr (memory write) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ramwr 0 1 - 0 0 1 0 1 1 0 0 (2ch) 1st parameter 1 1 d17-8 d7 d6 d5 d4 d3 d2 d1 d0 - O 1 1 O O O O O O O O O O nth parameter 1 1 d17-8 d7 d6 d5 d4 d3 d2 d1 d0 - note: - dont care, can be set to vddi or dgnd level description - when this command is accepted, the column register and the row register are reset to the start column/start row positions. -the start column/start row positions are different in accordance with madctl setting. (see section 9.12) -sending any other command can stop frame write. in all color modes, there is no restriction on length of parameters. -1. 176x220 memory base (gm = 00) 176x220x18-bit memory can be written by this command memory range: (0000h,0000h) -> (00afh, 00dbh) default status default value power on sequence contents of memory is set randomly s/w reset contents of memory is not cleared h/w reset contents of memory is not cleared
ST7773 ver. 2.0 2008-07-07 83 10.1.22 ramhd (2eh): memory read 2eh ramhd (memory read) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ramhd 0 1 - 0 0 1 0 1 1 1 0 (2eh) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 d17-8 d7 d6 d5 d4 d3 d2 d1 d0 - O 1 1 O O O O O O O O O O (n+1) th parameter 1 1 d17-8 d7 d6 d5 d4 d3 d2 d1 d0 - note: - dont care, can be set to vddi or dgnd level description -this command is used to transfer data from frame memory to mcu. -when this command is accepted, the column register a nd the row register are reset to the start column/start row positions. -the start column/start row positions are different in accordance with madctl setting. (see section 9.12) -then d[17:0] is read back from the frame memory and the column register and th e row register incremented as section 9.10.2. -frame read can be cancelled by sending any other command. -see section 9.8 data color coding for color coding (18-bit cases), when there is used 8, 9, 16 and 18-bit data lines for image data. default status default value power on sequence contents of memory is set randomly s/w reset contents of memory is not cleared h/w reset contents of memory is not cleared
ST7773 ver. 2.0 2008-07-07 84 10.1.25 ptlar (30h): partial area 30h ptlar (partial area) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ptlar 0 1 - 0 0 1 1 0 0 0 0 (30h) 1 st parameter 1 1 - psl15 psl14 psl13 psl12 psl11 psl10 psl9 psl8 2 nd parameter 1 1 - psl7 psl6 psl5 psl4 psl3 psl2 psl1 psl0 3 rd parameter 1 1 - pel15 pel14 pel13 pel12 pel11 pel10 pel9 pel8 4 th parameter 1 1 - pel7 pel6 pel5 pel4 pel3 pel2 pel1 pel0 note: - dont care, can be set to vddi or dgnd le vel description -this command defines the partial modes display ar ea. - there are 4 parameters associated with this command , the first defines the start row (psl) and the second the end row (pel), as illustrated in the figure s below. psl and pel refer to the frame memory row address counter. -if end row = start row then the partial area will be o ne row deep. default default value status psl [15:0] pel [15:0] power on sequence s/w reset h/w reset 0000h 00dbh - i f e n d row > st art ro w , w h en m a dc t l m l = 0 s t a rt ro w p s l [15:0] n o n - d is pl a y i n g ar ea p a rti a l di s p lay a r ea p e l [15:0] e nd r o w n o n - d i s p l a y ing ar ea - i f e n d row > st art ro w , w h en ma dc t l m l = 1 e nd r o w p e l [15:0] n o n - d is pl a y i n g ar ea p a rti a l di s p lay a r ea p s l [15:0] s t a rt ro w n o n - d i s p l a y ing ar ea - i f e n d row < st art ro w , w h en ma dc t l m l = 0 e nd r o w p e l [15:0] n o n - di s p lay ing ar ea p a rti a l d i s p la y ar ea p s l [15:0] s t a rt ro w pa rti a l d i s p la y ar ea
ST7773 ver. 2.0 2008-07-07 85 10.1.23 scrlar (33h): scroll area 33h scrlar (scrolll area) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ptlar 0 1 - 0 0 1 1 0 0 1 1 (33h) 1 st parameter 1 1 - tfa15 tfa 14 tfa 13 tfa 12 tfa 11 tfa 10 tfa 9 tfa 8 00h 2 nd parameter 1 1 - tfa 7 tfa 6 tfa 5 tfa 4 tfa 3 tfa 2 tfa 1 tfa 0 00h 3 rd parameter 1 1 - vsa15 vsa 14 vsa 13 vsa 12 vsa 11 vsa 10 vsa 9 vsa 8 4 th parameter 1 1 - vsa 7 vsa 6 vsa 5 vsa 4 vsa 3 vsa 2 vsa 1 vsa 0 5 th parameter 1 1 - bfa15 bfa 14 bfa 13 bfa 12 bfa 11 bfa 10 bfa 9 bfa 8 00h 6 th parameter 1 1 - bfa 7 bfa 6 bfa 5 bfa 4 bfa 3 bfa 2 bfa 1 bfa 0 00h note: - dont care, can be set to vddi or dgnd le vel description -this command defines the vertical scrolling area of t he display. when madctl ml=0 the 1 st & 2 nd parameter tfa [15:0] describes the top fixed area (i n no. of lines from top of the frame memory and display). the 3 rd & 4 th parameter vsa [15:0] describes the height of the vert ical scrolling are a (in no. of lines of the frame memory [not the display] from the vertical scrolling start address) the first line appears immediately after the bottom most line of the top fixed area. the 5 th & 6 th parameter bfa [15:0] describes the bottom fixed area ( in no. of lines from bottom of the frame memory and display). tfa, vsa and bfa refer to the frame memory row address. when madctl ml=1 the 1 st & 2 nd parameter tfa [15:0] describes the top fixed area (in no. of lines from bottom of the frame memory and display). the 3 rd & 4 th parameter vsa [15:0] describes the height of the vert ical scrolling area (in no. of lines of the frame memory [not the display] from the vertical scrolling start address) the first line appears immediately after the top mo st line of the top fixed area. the 5 th & 6 th parameter bfa [15:0] describes the bottom fixed area ( in no. of lines from top of the frame memory and display). see section 9.10.1 for details of the memory to displ ay mapping. -the condition is 0 Q (tfa+vsa+bfa) Q 220, otherwise scrolling mode is undefined. -in vertical scroll mode, madctl parameter mv should be set to 0-this only affects the frame memory write. default default value status tfa [15:0] vsa [15:0] bfa [15:0] power on sequence s/w reset h/w reset 0000h 00dbh t op - le f t (0,0) top fixed area tfa [15:0] scroll fixed area v s f a [15:0] first line read from b o tt o m f ixe d ar ea bfa [15:0] t op - le f t (0,0) bottom fixed area b f a [15:0] s c r ol l fi xe d ar ea vsfa [15:0] top fixed area t f a [15:0] first line read from frame memory
ST7773 ver. 2.0 2008-07-07 86 flow chart note: the frame memory window size must be defined correctly otherwise undesirable image will be displ ayed. 1. to enter vertical scroll mode legend normal mo de scrlar (33h) 1 st & 2 nd parameter: tfa[15:0] 3 rd & 4 th parameter vsa[15:0] 5 th & 6 th parameter bfa[15:0] c o m m a nd parameter display action mode sequential transfer c a set ( 2ah) 1 s t & 2 n d parameter xs[15:0] 3 rd & 4 th parameter xe[15:0] re d e f i n e s th e fram e memory window that the scroll data will be define only required for non-rolling scrolling raset (2 1 st & 2 nd parameter ys[15:0] 3 rd & 4 th parameter ye[15:0] madctl (36h) parameter: m y , mx , m v ,m l , rgb r a m rw (2c h) scr ol l i mage d a ta vscs a d ( 3 7 h) 1 s t & 2 n d parameter ss a[15:0]1 scro l l mo de opt i o n al C it may be necessary to redefine the frame memory write direction.
ST7773 ver. 2.0 2008-07-07 87 note: scroll mode can be exit by both the normal di splay mode on (13h) and partial mode on (12h) commands. 2 . co n tin u ous scr o ll normal mode caset (2ah) 1 st &2 nd parameter xs[15:0] 3 rd & 4 th parameter xe[15:0] raset (2bh) l ege n d command parameter display action mode sequential transfer 1 s t & 2 n d parameter ys[15:0] 3 rd & 4 th parameter ye[15:0] r am rw (2c h) only require d for non-rollin g scrolling scro l l i mage da ta vscs a d (37 h) 1 s t & 2 nd parameter ssa[15:0]1 3. t o e x it ve rtical s c r o ll mo de scro l l m ode disoff (28h) noron ( 1 3 h ) / p t lon (12 h) opt i o n - to prevent tearing effect image display s c r ol l m o d e o ff r am rw (2c h) image data d1[17:0],d2[17:0] dn[17:0] d i son (29 h)
ST7773 ver. 2.0 2008-07-07 88 10.1.24 teoff (34h): tearing effect line off 34h teoff (tearing effect line off) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) teoff 0 1 - 0 0 1 1 0 1 0 0 (34h) 1st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command is used to turn off (active low) the t earing effect output signal from the te signal line. default status default value rcm1,rcm0 = 00,1x rcm1,rcm0 = 01 power on sequence s/w reset h/w reset off on 10.1.25 teon (35h): tearing effect line on 35h teon (tearing effect line on) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) teon 0 1 - 0 0 1 1 0 1 0 1 (35h) 1st parameter 1 1 - 0 0 0 0 0 0 0 telom note: - dont care, can be set to vddi or dgnd le vel description -this command is used to turn on the tearing effect output signal from the te signal line. -this output is not affected by changing madctl bit ml. -the tearing effect line on has one parameter, which describes the mode of the tearing effect output line. (-=dont care). when m=0: when m=1: note: during sleep in mode with tearing effect line on, tearing effect output pin will be active low. default status default value power on sequence s/w reset h/w reset tearing effect off & telom=0 tearing effect on & telom=0 ve rtical ti m e s c a l e t vd l t v dh the tearing effect output line consists of v - blanking information only. the tearing effect output line co nsists of both v - blanking and h - blinking information. ve rtical time scale t vd l t v dh
ST7773 ver. 2.0 2008-07-07 89 10.1.26 madctl (36h): memory data access control 36h madctl (memory data access control) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) madctl 0 1 - 0 0 1 1 0 1 1 0 (36h) 1st parameter 1 1 - my mx mv ml rgb mh 0 0 00h note: - dont care, can be set to vddi or dgnd le vel description -this command defines read/ write scanning directio n of frame memory. -bit assignment bit name description my row address order mx column address order mv row/column exchange these 3bits controls mcu to memory write/read direction. (see section 9.12) ml vertical refresh order lcd vertical refresh direction control 0 = lcd vertical refresh top to bottom 1 = lcd vertical refresh bottom to top rgb rgb-bgr order color selector switch control 0 = r g b color filter panel, 1 = b g r color filter panel) mh horizontal refresh order lcd horizontal refresh direction control 0 = lcd horizontal refresh left to right 1 = lcd horizontal refresh right to left sen t 3 r d sent 2nd sent first me m o r y d i s pl ay sent last sen t la s t m l: v ert i cal refres h or d er memory display sent first sent 2nd se n t 3rd t op - le f t (0,0) m l = 0 t op - le f t (0,0) m l = 1 rgb: rgb - bgr order r g b s ig1 rgb = 0 driver ic r g b s ig2 r g b s ig 176 r g b si g 1 rg b = 1 driver ic r g b sig 2 r g b sig 176 s ig1 r g b r g s ig2 r g b r g b lcd p an el s ig 176 r g b r g b si g 1 b g r si g 2 b g r b g r l cd pa n el sig 176 b g r b g r r g b r g b r g b r g b r g b r g b b g r b g r b g r b g r b g r b g r r g b r g b r g b r g b r g b r g b
ST7773 ver. 2.0 2008-07-07 90 description default status default value power on sequence my=0,mx=0,mv=0,ml=0,rgb=0, mh=0 s/w reset no change h/w reset my=0,mx=0,mv=0,ml=0,rgb=0, mh=0 t op - le f t (0,0) m h: h o r i z o nt al refres h order top-left (0,0) me m o r y me m o r y ml = 0 m l = 1 t o p - le f t (0,0) d i s p l ay t op - le f t (0,0) d i s p l ay sent first sent 2nd sent 3rd sent last sent last sent 3rd sent 2nd sent first
ST7773 ver. 2.0 2008-07-07 91 10.1.27 vscsad (37h): vertical scroll start address of ram 37h vscsad (vertical scroll start address of ram) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) vscsad 0 1 - 0 0 1 1 0 1 1 1 (37h) 1 st parameter 1 1 - 0 0 0 0 0 0 0 ssa8 00h 2 nd parameter 1 1 ssa7 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssa0 00h note: - dont care, can be set to vddi or dgnd le vel description -this command is used together with verti cal scrolling definition (33h). these two commands d escribe the scrolling area and the scrolling mode. - the vertical scrolling start address command has one p arameter which describes which line in the frame memory will be written as the first line after the last line of the top fixed area on the display as il lustrated below: -this command start the scrolling. -exit from v-scrolling mode by commands partial mod e on (12h) or normal mode on (13h). when madctl ml= 0 example: when top fixed area=bottom fixed area=00, vertical scro lling area=220 and vertical scrolling pointer ssa= 3. when madctl ml = 1 example: when top fixed area= bottom fixed area=00, vertical scrolling area=220 and ssa= 3 note: -when new pointer position and picture data a re sent, the result on the display will happen at t he next panel scan to avoid tearing effect. -ssa refers to the frame memory scan address. default status default value power on sequence 0000h s/w reset 0000h h/w reset 0000h t op - le f t (0,0) ssa[15:0] s c r ol l s t a rt a ddr e ss (e x a mp l e) scan address memory display 0 g1 1 g2 2 g3 3 g4 O | O | 218 g219 219 g220 t op - le f t (0,0) ssa[15:0] s c r ol l s t a rt a ddr e ss (e x am pl e) scan address memory display 219 g1 218 g2 O g3 O g4 3 | 2 | 1 g219 0 g220
ST7773 ver. 2.0 2008-07-07 92 10.1.28 idmoff (38h): idle mode off 38h idmoff (idle mode off) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) idmoff 0 1 - 0 0 1 1 1 0 0 0 (38h) 1st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command is used to recover from idle mode on. -in the idle off mode, 1. lcd can display 4096, 65k or 262k colors. 2. normal frame frequency is applied. default status default value power on sequence idle mode off s/w reset idle mode off h/w reset idle mode off 10.1.29 idmon (39h): idle mode on 39h idmon (idle mode on) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) idmoff 0 1 - 0 0 1 1 1 0 0 1 (39h) 1st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command is used to enter into idle mode on. -there will be no abnormal visible effect on the di splay mode change transition. -in the idle on mode, 1. color expression is reduced. the primary and the secondary colors using msb of each r,g and b in the frame memory, 8 color depth data is displayed. 2. 8-color mode frame frequency is applied. 3. exit from idmon by idle mode off (38h) command color r 5 r 4 r 3 r 2 r 1 r 0 g 5 g 4 g 3 g 2 g 1 g 0 b 5 b 4 b 3 b 4 b 1 b 0 black 0xxxxx 0xxxxx 0xxxxx blue 0xxxxx 0xxxxx 1xxxxx red 1xxxxx 0xxxxx 0xxxxx magenta 1xxxxx 0xxxxx 1xxxxx green 0xxxxx 1xxxxx 0xxxxx cyan 0xxxxx 1xxxxx 1xxxxx yellow 1xxxxx 1xxxxx 0xxxxx white 1xxxxx 1xxxxx 1xxxxx default status default value power on sequence idle mode off s/w reset idle mode off h/w reset idle mode off t op - le f t (0, 0 ) (e x amp l e) me m o ry di s p lay
ST7773 ver. 2.0 2008-07-07 93 10.1.30 colmod (3ah): interface pixel format 3ah colmod (3ah): interface pixel format inst / para d/cx wrx rdx d17- 8 d7 d6 d5 d4 d3 d2 d1 d0 (code) colmod 0 1 - 0 0 1 1 1 0 1 0 (3ah) 1st parameter 1 1 - 0 1 1 0 0 ifpf2 ifpf1 ifpf0 66h note: - dont care, can be set to vddi or dgnd le vel description this command is used to define the format of rgb pic ture data, which is to be transferred via the mcu interface and rgb interface. the formats are shown in the table: ifpf[2:0] mcu interface color format 011 3 12-bit/pixel 101 5 16-bit/pixel 110 6 18-bit/pixel 111 7 no used others are no define and invalid note1: in 12-bit/pixel, 16-bit/pixel or 18-bit/pixe l mode, the lut is applied to transfer data into th e frame memory. note 2: when vipf[3:0]=1110,6-bit data width of 3 -times transfer is used to transmit 1 pixel data wi th the 18-bit color depth information. default status default value vipf[3:0] power on sequence 06h(18-bit/pixel) s/w reset no change h/w reset 06h(18-bit/pixel) 10.1.31 rdid1 (dah): read id1 value dah rdid1 (read id1 value) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rdid1 0 1 - 1 1 0 1 1 0 1 0 (dah) 1st parameter 1 1 - - - - - - - - - - 2nd parameter 1 1 - id17 id16 id15 id14 id13 id12 id11 id10 note: - dont care, can be set to vddi or dgnd le vel description -this read byte returns 8-bit lcd modules manufact urer id -the 1 st parameter is dummy data -the 2 nd parameter (id17 to id10): lcd modules manufacture r id. note: see command rddid (04h), 2 nd parameter. default status default value power on sequence - s/w reset 29h h/w reset 29h
ST7773 ver. 2.0 2008-07-07 94 10.1.32 rdid2 (dbh): read id2 value dbh rdid2 (read id2 value) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rdid2 0 1 - 1 1 0 1 1 0 1 1 (dbh) 1st parameter 1 1 - - - - - - - - - - 2nd parameter 1 1 - 1 id26 id25 id24 id23 id22 id21 id20 note: - dont care, can be set to vddi or dgnd le vel description -this read byte returns 8-bit lcd module/driver ver sion id -the 1 st parameter is dummy data -the 2 nd parameter (id26 to id20): lcd module/driver version id -parameter range: id=80h to ffh default status default value power on sequence - s/w reset 81h h/w reset 81h
ST7773 ver. 2.0 2008-07-07 95 10.2.1 frmctr1 (b1h): frame rate control (in normal mode/ full colors) b1h frmctr1 (frame rate control) inst / para d/cx wrx rdx d1 7-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) frmctr1 0 1 - 1 0 1 1 0 0 0 1 (b1h) 1st parameter 1 1 - rtna[7:0] 3bh 2nd parameter 1 1 - fpa[4:0] 04h 3rd parameter 1 1 - bpa[4:0] 03h nth parameter 1 1 - rtna_vsync[7:0] 38h note: - dont care description -set the frame frequency of the full colors normal mode,recommend to set under 110hz. -the frame frequency need to meet 60hz 5% in this mode rtna[7:0] frame rate rtna[7:0] frame rate 0100000 32 110 1010000 80 44 0100001 33 107 1010001 81 43 0100010 34 104 1010010 82 43 0100011 35 101 1010011 83 42 0100100 36 98 1010100 84 42 0100101 37 95 1010101 85 41 0100110 38 93 1010110 86 41 0100111 39 90 1010111 87 41 0101000 40 88 1011000 88 40 0101001 41 86 1011001 89 40 0101010 42 84 1011010 90 39 0101011 43 82 1011011 91 39 0101100 44 80 1011100 92 38 0101101 45 78 1011101 93 38 0101110 46 77 1011110 94 37 0101111 47 75 1011111 95 37 0110000 48 73 1100000 96 37 0110001 49 72 1100001 97 36 0110010 50 70 1100010 98 36 0110011 51 69 1100011 99 36 0110100 52 68 1100100 100 35 0110101 53 66 1100101 101 35 0110110 54 65 1100110 102 35 0110111 55 64 1100111 103 34 0111000 56 63 1101000 104 34 0111001 57 62 1101001 105 34 0111010 58 61 1101010 106 33 0111011 59 60 1101011 107 33 0111100 60 59 1101100 108 33 0111101 61 58 1101101 109 32 0111110 62 57 1101110 110 32 0111111 63 56 1101111 111 32 1000000 64 55 1110000 112 31 1000001 65 54 1110001 113 31 1000010 66 53 1110010 114 31 1000011 67 52 1110011 115 31 1000100 68 52 1110100 116 30 1000101 69 51 1110101 117 30 1000110 70 50 1110110 118 30 1000111 71 49 1110111 119 30 1001000 72 49 1111000 120 29 1001001 73 48 1111001 121 29 1001010 74 48 1111010 122 29 1001011 75 47 1111011 123 29 1001100 76 46 1111100 124 28 1001101 77 46 1111101 125 28 1001110 78 45 1111110 126 28
ST7773 ver. 2.0 2008-07-07 96 1001111 79 45 1111111 127 28 note: osc output fre. is 800khz, fpa=04h and bpa=0 3h fpa[4:0] timing bpa[4:0] timing 00000 0 0 line 00000 0 0 line 00001 1 1 line 00001 1 1 line 00010 2 2 lines 00010 2 2 lines 00011 3 3 lines 00011 3 3 lines 00100 4 4 lines 00100 4 4 lines 00101 5 5 lines 00101 5 5 lines 00110 6 6 lines 00110 6 6 lines 00111 7 7 lines 00111 7 7 lines 01000 8 8 lines 01000 8 8 lines 01001 9 9 lines 01001 9 9 lines 01010 10 10 lines 01010 10 10 lines 01011 11 11 lines 01011 11 11 lines 01100 12 12 lines 01100 12 12 lines 01101 13 13 lines 01101 13 13 lines 01110 14 14 lines 01110 14 14 lines 01111 15 15 lines 01111 15 15 lines 10000 16 16 lines 10000 16 16 lines 10001 17 17 lines 10001 17 17 lines 10010 18 18 lines 10010 18 18 lines 10011 19 19 lines 10011 19 19 lines 10100 20 20 lines 10100 20 20 lines 10101 21 21 lines 10101 21 21 lines 10110 22 22 lines 10110 22 22 lines 10111 23 23 lines 10111 23 23 lines 11000 24 24 lines 11000 24 24 lines 11001 25 25 lines 11001 25 25 lines 11010 26 26 lines 11010 26 26 lines 11011 27 27 lines 11011 27 27 lines 11100 28 28 lines 11100 28 28 lines 11101 29 29 lines 11101 29 29 lines 11110 30 30 lines 11110 30 30 lines 11111 31 31 lines 11111 31 31 lines default status default value power on sequence 3b/04/03/38 h s/w reset - h/w reset 3b/04/03/38 h
ST7773 ver. 2.0 2008-07-07 97 10.2.2 frmctr2 (b2h): frame rate control (in idle m ode/ 8-colors) b2h frmctr2 (frame rate control) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) frmctr2 0 1 - 1 0 1 1 0 0 1 0 (b2h) 1st parameter 1 1 - rtnb[7:0] 3bh 2nd parameter 1 1 - - - - fpb[4:0] 04h 3rd parameter 1 1 - - - - bpb[4:0] 03h note: - dont care description -set the frame frequency of the full colors idle mo de, ,recommend to set under 110hz. -the frame frequency need to meet 60hz 5% in this mode rtnb[7:0] frame rate rtnb[7:0] frame rate 0100000 32 110 1010000 80 44 0100001 33 107 1010001 81 43 0100010 34 104 1010010 82 43 0100011 35 101 1010011 83 42 0100100 36 98 1010100 84 42 0100101 37 95 1010101 85 41 0100110 38 93 1010110 86 41 0100111 39 90 1010111 87 41 0101000 40 88 1011000 88 40 0101001 41 86 1011001 89 40 0101010 42 84 1011010 90 39 0101011 43 82 1011011 91 39 0101100 44 80 1011100 92 38 0101101 45 78 1011101 93 38 0101110 46 77 1011110 94 37 0101111 47 75 1011111 95 37 0110000 48 73 1100000 96 37 0110001 49 72 1100001 97 36 0110010 50 70 1100010 98 36 0110011 51 69 1100011 99 36 0110100 52 68 1100100 100 35 0110101 53 66 1100101 101 35 0110110 54 65 1100110 102 35 0110111 55 64 1100111 103 34 0111000 56 63 1101000 104 34 0111001 57 62 1101001 105 34 0111010 58 61 1101010 106 33 0111011 59 60 1101011 107 33 0111100 60 59 1101100 108 33 0111101 61 58 1101101 109 32 0111110 62 57 1101110 110 32 0111111 63 56 1101111 111 32 1000000 64 55 1110000 112 31 1000001 65 54 1110001 113 31 1000010 66 53 1110010 114 31 1000011 67 52 1110011 115 31 1000100 68 52 1110100 116 30 1000101 69 51 1110101 117 30 1000110 70 50 1110110 118 30 1000111 71 49 1110111 119 30 1001000 72 49 1111000 120 29 1001001 73 48 1111001 121 29 1001010 74 48 1111010 122 29 1001011 75 47 1111011 123 29 1001100 76 46 1111100 124 28 1001101 77 46 1111101 125 28 1001110 78 45 1111110 126 28
ST7773 ver. 2.0 2008-07-07 98 1001111 79 45 1111111 127 28 note: osc output fre. is 800khz, fpb=04h and bpb=0 3h fpb[4:0] timing bpb[4:0] timing 00000 0 0 line 00000 0 0 line 00001 1 1 line 00001 1 1 line 00010 2 2 lines 00010 2 2 lines 00011 3 3 lines 00011 3 3 lines 00100 4 4 lines 00100 4 4 lines 00101 5 5 lines 00101 5 5 lines 00110 6 6 lines 00110 6 6 lines 00111 7 7 lines 00111 7 7 lines 01000 8 8 lines 01000 8 8 lines 01001 9 9 lines 01001 9 9 lines 01010 10 10 lines 01010 10 10 lines 01011 11 11 lines 01011 11 11 lines 01100 12 12 lines 01100 12 12 lines 01101 13 13 lines 01101 13 13 lines 01110 14 14 lines 01110 14 14 lines 01111 15 15 lines 01111 15 15 lines 10000 16 16 lines 10000 16 16 lines 10001 17 17 lines 10001 17 17 lines 10010 18 18 lines 10010 18 18 lines 10011 19 19 lines 10011 19 19 lines 10100 20 20 lines 10100 20 20 lines 10101 21 21 lines 10101 21 21 lines 10110 22 22 lines 10110 22 22 lines 10111 23 23 lines 10111 23 23 lines 11000 24 24 lines 11000 24 24 lines 11001 25 25 lines 11001 25 25 lines 11010 26 26 lines 11010 26 26 lines 11011 27 27 lines 11011 27 27 lines 11100 28 28 lines 11100 28 28 lines 11101 29 29 lines 11101 29 29 lines 11110 30 30 lines 11110 30 30 lines 11111 31 31 lines 11111 31 31 lines default status default value power on sequence 3b/04/03 h s/w reset - h/w reset 3b/04/03 h
ST7773 ver. 2.0 2008-07-07 99 10.2.3 frmctr3 (b3h): frame rate control (in partia l mode/ full colors) b3h frmctr3 (frame rate control) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) frmctr3 0 1 - 1 0 1 1 0 0 1 1 (b3h) 1st parameter 1 1 - rtnc[7:0] 3bh 2nd parameter 1 1 - fpc[4:0] 04h 3rd parameter 1 1 - bpc[4:0] 03h note: - dont care description -set the frame frequency of the full colors partial mode,recommend to set under 110hz. -the frame frequency need to meet 60hz 5% in this mode rtnc[7:0] frame rate rtnc[7:0] frame rate 0100000 32 110 1010000 80 44 0100001 33 107 1010001 81 43 0100010 34 104 1010010 82 43 0100011 35 101 1010011 83 42 0100100 36 98 1010100 84 42 0100101 37 95 1010101 85 41 0100110 38 93 1010110 86 41 0100111 39 90 1010111 87 41 0101000 40 88 1011000 88 40 0101001 41 86 1011001 89 40 0101010 42 84 1011010 90 39 0101011 43 82 1011011 91 39 0101100 44 80 1011100 92 38 0101101 45 78 1011101 93 38 0101110 46 77 1011110 94 37 0101111 47 75 1011111 95 37 0110000 48 73 1100000 96 37 0110001 49 72 1100001 97 36 0110010 50 70 1100010 98 36 0110011 51 69 1100011 99 36 0110100 52 68 1100100 100 35 0110101 53 66 1100101 101 35 0110110 54 65 1100110 102 35 0110111 55 64 1100111 103 34 0111000 56 63 1101000 104 34 0111001 57 62 1101001 105 34 0111010 58 61 1101010 106 33 0111011 59 60 1101011 107 33 0111100 60 59 1101100 108 33 0111101 61 58 1101101 109 32 0111110 62 57 1101110 110 32 0111111 63 56 1101111 111 32 1000000 64 55 1110000 112 31 1000001 65 54 1110001 113 31 1000010 66 53 1110010 114 31 1000011 67 52 1110011 115 31 1000100 68 52 1110100 116 30 1000101 69 51 1110101 117 30 1000110 70 50 1110110 118 30 1000111 71 49 1110111 119 30 1001000 72 49 1111000 120 29 1001001 73 48 1111001 121 29 1001010 74 48 1111010 122 29 1001011 75 47 1111011 123 29 1001100 76 46 1111100 124 28 1001101 77 46 1111101 125 28 1001110 78 45 1111110 126 28 1001111 79 45 1111111 127 28 note: osc output fre. is 800khz, fpc=04h and bpc=0 3h
ST7773 ver. 2.0 2008-07-07 100 fpc[4:0] timing bpc[4:0] timing 00000 0 0 line 00000 0 0 line 00001 1 1 line 00001 1 1 line 00010 2 2 lines 00010 2 2 lines 00011 3 3 lines 00011 3 3 lines 00100 4 4 lines 00100 4 4 lines 00101 5 5 lines 00101 5 5 lines 00110 6 6 lines 00110 6 6 lines 00111 7 7 lines 00111 7 7 lines 01000 8 8 lines 01000 8 8 lines 01001 9 9 lines 01001 9 9 lines 01010 10 10 lines 01010 10 10 lines 01011 11 11 lines 01011 11 11 lines 01100 12 12 lines 01100 12 12 lines 01101 13 13 lines 01101 13 13 lines 01110 14 14 lines 01110 14 14 lines 01111 15 15 lines 01111 15 15 lines 10000 16 16 lines 10000 16 16 lines 10001 17 17 lines 10001 17 17 lines 10010 18 18 lines 10010 18 18 lines 10011 19 19 lines 10011 19 19 lines 10100 20 20 lines 10100 20 20 lines 10101 21 21 lines 10101 21 21 lines 10110 22 22 lines 10110 22 22 lines 10111 23 23 lines 10111 23 23 lines 11000 24 24 lines 11000 24 24 lines 11001 25 25 lines 11001 25 25 lines 11010 26 26 lines 11010 26 26 lines 11011 27 27 lines 11011 27 27 lines 11100 28 28 lines 11100 28 28 lines 11101 29 29 lines 11101 29 29 lines 11110 30 30 lines 11110 30 30 lines 11111 31 31 lines 11111 31 31 lines default status default value power on sequence 3b/04/03 h s/w reset - h/w reset 3b/04/03 h
ST7773 ver. 2.0 2008-07-07 101 10.2.4 invctr (b4h): display inversion control b4h invctr (display inversion control) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) invctr 0 1 - 1 0 1 1 0 1 0 0 (b4h) 1st parameter 1 1 - 0 0 0 0 0 nla nlb nlc note: - dont care description -display inversion mode control -nla: inversion setting in full colors normal mode ( normal mode on) nla inversion setting in full colors normal mode 0 line inversion 1 frame inversion -nlb: inversion setting in idle mode (idle mode on) nlb inversion setting in idle mode 0 line inversion 1 frame inversion -nlc: inversion setting in full colors partial mode ( partial mode on / idle mode off) nlc inversion setting in full colors partial mode 0 line inversion 1 frame inversion default status default value nla nlb nlc b4h power on sequence 0d 1d 0d 02h s/w reset no change no change no change no change h/w reset 0d 1d 0d 02h
ST7773 ver. 2.0 2008-07-07 102 10.2.5 disset5 (b6h): display function set 5 b6h disset (display function set 5) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) disset5 0 1 - 1 0 1 1 0 1 1 0 (b6h) 1st parameter 1 1 - 0 0 no1 no0 sdt1 sdt0 eq1 eq0 15h 2nd parameter 1 1 - 0 0 0 0 ptg1 ptg0 pt1 pt0 00h note: - dont care description -1 st parameter: set output waveform relation. -no[1:0]: set the amount of non-overlap of the gate output no[1:0] amount of non-overlap of the gate output refer the internal oscillator refer the pclk 00 0 no 4 clock cycle 01 1 1 clock cycle 16 clock cycle 10 2 4 clock cycle 24 clock cycle 11 3 6 clock cycle 32 clock cycle -sdt[1:0]: set delay amount from gate signal falling edge of the source output. sdt[1:0] amount of non-overlap of the gate output refer the internal oscillator refer the pclk 00 0 no 4 clock cycle 01 1 1 clock cycle 8 clock cycle 10 2 2 clock cycle 12clock cycle 11 3 3 clock cycle 16 clock cycle -eq[1:0]: set the equalizing period -2 nd parameter: set the output waveform in non-display ar ea. -ptg[1:0]: determine gate output in a non-display ar ea in the partial mode -pt[1:0]: determine source /vcom output in a non-disp lay area in the partial mode eq[1:0] amount of non-overlap of the gate output refer the internal oscillator refer the pclk 00 0 no eq no eq 01 1 2 clock cycle 4 clock cycle 10 2 4 clock cycle 16 clock cycle 11 3 6 clock cycle 24 clock cycle ptg[1:0] gate output in a non-display area 00 0 normal scan 01 1 fix on vgl 10 2 fix on vgl 11 3 fix on vgl pt[1:0] source output on non-display area vcom output on non-display area positive negative positive negative 00 0 v63 v0 vcoml vcomh 01 1 v0 v63 vcoml vcomh 10 2 agnd agnd agnd agnd 11 3 hi-z hi-z agnd agnd gn gate non-overlap period gn+1 s n vcom delay ti m e f or source output eq per i od
ST7773 ver. 2.0 2008-07-07 103 default status default value no[1:0] std[1:0] eq[1:0] ptg[1:0] pt[1:0] power on sequence 01h 01h 01h 01h 10h s/w reset 01h 01h 01h 01h 10h h/w reset 01h 01h 01h 01h 10h
ST7773 ver. 2.0 2008-07-07 104 10.2.8 pwctr1 (c0h): power control 1 c0h pwctr1 (power control 1) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) pwctr1 0 1 - 1 1 0 0 0 0 0 0 (c0h) 1st parameter 1 1 - 0 0 0 vrh4 vrh3 vrh2 vrh1 vrh0 note: - dont care description -set the gvdd and vci1 voltage vrh[4:0] gvdd 00000 0 5.00 00001 1 4.75 00010 2 4.70 00011 3 4.65 00100 4 4.60 00101 5 4.55 00110 6 4.50 00111 7 4.45 01000 8 4.40 01001 9 4.35 01010 10 4.30 01011 11 4.25 01100 12 4.20 01101 13 4.15 01110 14 4.10 01111 15 4.05 10000 16 4.00 10001 17 3.95 10010 18 3.90 10011 19 3.85 10100 20 3.80 10101 21 3.75 10110 22 3.70 10111 23 3.65 11000 24 3.60 11001 25 3.55 11010 26 3.50 11011 27 3.45 11100 28 3.40 11101 29 3.35 11110 30 3.25 11111 31 3.00 default status default value tm lc type vrh[4:0] power on sequence 05h s/w reset 05h h/w reset 05h
ST7773 ver. 2.0 2008-07-07 105 10.2.9 pwctr2 (c1h): power control 2 c1h pwctr2 (power control 2) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) pwctr2 0 1 - 1 1 0 0 0 0 0 1 (c1h) 1st parameter 1 1 vgh3 vgh2 vgh1 vgh0 vgl3 vgl2 vgl1 vgl0 bbh note: - dont care description -set the vgh and vgl supply power level vgh[3:0]/vgl[3:0] vgh vgl 0000 0 10 -5.5 0001 1 10.5 -6 0010 2 11 -7.5 0011 3 11.5 -8 0100 4 12 -8.5 0101 5 12.5 -9 0110 6 13 -9.5 0111 7 13.5 -10 1000 8 14 -10.5 1001 9 14.5 -11 1010 10 15 -11.5 1011 11 15.5 -12 1100 12 16 -12.5 1101 13 16.5 -13 1110 14 x -13.5 1111 15 x x unit(v) default status default value vgh[3:0] vgl[3:0] power on sequence - - s/w reset 0bh 0bh h/w reset 0bh 0bh
ST7773 ver. 2.0 2008-07-07 106 10.2.10 pwctr3 (c2h): power control 3 (in normal mo de/ full colors) c2h pwctr3 (power control 3) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) pwctr3 0 1 - 1 1 0 0 0 0 1 0 (c2h) 1st parameter 1 1 - 0 0 0 0 0 apa2 apa1 apa0 04h note: - dont care description -set the amount of current in operational amplifier in normal mode/full colors. -adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. apa[2:0] amount of current in operational amplifier 000 0 operation of the operational amplifier stops 001 1 small 010 2 medium low 011 3 medium 100 4 medium high 101 5 large 110 6 reserved 111 7 reserved default status default value apa[2:0] power on sequence - s/w reset 04h h/w reset 04h 10.2.11 pwctr4 (c3h): power control 4 (in idle mode / 8-colors) c3h pwctr4 (power control 4) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) pwctr4 0 1 - 1 1 0 0 0 0 1 1 (c3h) 1st parameter 1 1 - 0 0 0 0 0 apb2 apb1 apb0 note: - dont care description -set the amount of current in operational amplifier in idle mode/8 colors. -adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. apb[2:0] amount of current in operational amplifier 000 0 operation of the operational amplifier stops 001 1 small 010 2 medium low 011 3 medium 100 4 medium high 101 5 large 110 6 reserved 111 7 reserved default status default value apb[2:0] power on sequence - s/w reset 04h h/w reset 04h
ST7773 ver. 2.0 2008-07-07 107 10.2.12 pwctr5 (c4h): power control 5 (in partial m ode/ full-colors) c4h pwctr5 (power control 5) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) pwctr5 0 1 - 1 1 0 0 0 1 0 0 (c4h) 1st parameter 1 1 - 0 0 0 0 0 apc2 apc1 apc0 04h note: - dont care description -set the amount of current in operational amplifier in partial mode/ full-colors. -adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. apc[2:0] amount of current in operational amplifier 000 0 operation of the operational amplifier stops 001 1 small 010 2 medium low 011 3 medium 100 4 medium high 101 5 large 110 6 reserved 111 7 reserved default status default value apc[2:0] power on sequence - s/w reset 04h h/w reset 04h
ST7773 ver. 2.0 2008-07-07 108 10.2.13 vmctr1 (c5h): vcom control 1 c5h vmctr1 (vcom control 1) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) vmctr1 0 1 - 1 1 0 0 0 1 0 1 (c5h) 1st parameter 1 1 - 0 vmh6 vmh5 vmh 4 vmh 3 vmh 2 vmh 1 vmh 0 3ch 2nd parameter 1 1 - 0 vml 6 vml 5 vml 4 vml 3 vml 2 vml 1 vml 0 3ch note: - dont care description -set vcomh voltage vmh[6:0] vcomh vmh[6:0] vcomh vmh[6:0] vcomh vmh[6:0] vcomh 0000000 0 2.500 0011011 27 3.175 0110110 54 3.850 1010001 81 4.525 0000001 1 2.525 0011100 28 3.200 0110111 55 3.875 1010010 82 4.550 0000010 2 2.550 0011101 29 3.225 0111000 56 3.900 1010011 83 4.575 0000011 3 2.575 0011110 30 3.250 0111001 57 3.925 1010100 84 4.600 0000100 4 2.600 0011111 31 3.275 0111010 58 3.950 1010101 85 4.625 0000101 5 2.625 0100000 32 3.300 0111011 59 3.975 1010110 86 4.650 0000110 6 2.650 0100001 33 3.325 0111100 60 4.000 1010111 87 4.675 0000111 7 2.675 0100010 34 3.350 0111101 61 4.025 1011000 88 4.700 0001000 8 2.700 0100011 35 3.375 0111110 62 4.050 1011001 89 4.725 0001001 9 2.725 0100100 36 3.400 0111111 63 4.075 1011010 90 4.750 0001010 10 2.750 0100101 37 3.425 1000000 64 4.100 1011011 91 4.775 0001011 11 2.775 0100110 38 3.450 1000001 65 4.125 1011100 92 4.800 0001100 12 2.800 0100111 39 3.475 1000010 66 4.150 1011101 93 4.825 0001101 13 2.825 0101000 40 3.500 1000011 67 4.175 1011110 94 4.850 0001110 14 2.850 0101001 41 3.525 1000100 68 4.200 1011111 95 4.875 0001111 15 2.875 0101010 42 3.550 1000101 69 4.225 1100000 96 4.900 0010000 16 2.900 0101011 43 3.575 1000110 70 4.250 1100001 97 4.925 0010001 17 2.925 0101100 44 3.600 1000111 71 4.275 1100010 98 4.950 0010010 18 2.950 0101101 45 3.625 1001000 72 4.300 1100011 99 4.975 0010011 19 2.975 0101110 46 3.650 1001001 73 4.325 1100100 100 5.000 0010100 20 3.000 0101111 47 3.675 1001010 74 4.350 1100101 101 0010101 21 3.025 0110000 48 3.700 1001011 75 4.375 | 0010110 22 3.050 0110001 49 3.725 1001100 76 4.400 1111111 127 not permitted 0010111 23 3.075 0110010 50 3.750 1001101 77 4.425 0011000 24 3.100 0110011 51 3.775 1001110 78 4.450 0011001 25 3.125 0110100 52 3.800 1001111 79 4.475 0011010 26 3.150 0110101 53 3.825 1010000 80 4.500 -set vcoml voltage vml[6:0] vcoml vml[6:0] vcoml vml[6:0] vcoml vml[6:0] vcoml 0000000 0 -2.500 0011011 27 -1.825 0110110 54 -1.150 1010001 81 -0.475 0000001 1 -2.475 0011100 28 -1.800 0110111 55 -1.125 1010010 82 -0.450 0000010 2 -2.450 0011101 29 -1.775 0111000 56 -1.100 1010011 83 -0.425 0000011 3 -2.425 0011110 30 -1.750 0111001 57 -1.075 1010100 84 -0.400 0000100 4 -2.400 0011111 31 -1.725 0111010 58 -1.050 1010101 85 -0.375 0000101 5 -2.375 0100000 32 -1.700 0111011 59 -1.025 1010110 86 -0.350 0000110 6 -2.350 0100001 33 -1.675 0111100 60 -1.000 1010111 87 -0.325 0000111 7 -2.325 0100010 34 -1.650 0111101 61 -0.975 1011000 88 -0.300 0001000 8 -2.300 0100011 35 -1.625 0111110 62 -0.950 1011001 89 -0.275 0001001 9 -2.275 0100100 36 -1.600 0111111 63 -0.925 1011010 90 -0.250 0001010 10 -2.250 0100101 37 -1.575 1000000 64 -0.900 1011011 91 -0.225 0001011 11 -2.225 0100110 38 -1.550 1000001 65 -0.875 1011100 92 -0.200 0001100 12 -2.200 0100111 39 -1.525 1000010 66 -0.850 1011101 93 -0.175 0001101 13 -2.175 0101000 40 -1.500 1000011 67 -0.825 1011110 94 -0.150 0001110 14 -2.150 0101001 41 -1.475 1000100 68 -0.800 1011111 95 -0.125 0001111 15 -2.125 0101010 42 -1.450 1000101 69 -0.775 1100000 96 -0.100 0010000 16 -2.100 0101011 43 -1.425 1000110 70 -0.750 1100001 97 -0.075 0010001 17 -2.075 0101100 44 -1.400 1000111 71 -0.725 1100010 98 -0.050 0010010 18 -2.050 0101101 45 -1.375 1001000 72 -0.700 1100011 99 -0.025 0010011 19 -2.025 0101110 46 -1.350 1001001 73 -0.675 1100100 100 0.000 0010100 20 -2.000 0101111 47 -1.325 1001010 74 -0.650 1100101 101 0010101 21 -1.975 0110000 48 -1.300 1001011 75 -0.625 | 0010110 22 -1.950 0110001 49 -1.275 1001100 76 -0.600 1111111 127 not permitted 0010111 23 -1.925 0110010 50 -1.250 1001101 77 -0.575 0011000 24 -1.900 0110011 51 -1.225 1001110 78 -0.550 0011001 25 -1.875 0110100 52 -1.200 1001111 79 -0.525 0011010 26 -1.850 0110101 53 -1.175 1010000 80 -0.500
ST7773 ver. 2.0 2008-07-07 109 default status default value lcm = 01 tm lc type vmh[6:0] / vml[6:0] power on sequence - s/w reset 3ch / 3c h h/w reset 3ch / 3ch 10.2.14 vmofctr (c7h): vcom offset control c7h vmofctr (vcom offset control) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) vmofctr 0 1 - 1 1 0 0 0 1 1 1 (c7h) 1st parameter 1 1 - 0 vmf6 vmf5 vmf4 vmf3 vmf2 vmf1 vmf0 3ch note: - dont care, can be set to vddi or dgnd le vel description -set vcom voltage level for reduce the flicker issue vmf[6:0] vcomh output level vcoml output level 4 vmh-64d vml-60d 5 vmh-63d vml-59d 6 vmh-62d vml-58d | | | 58 vmh-2d vml-2d 59 vmh-1d vml-1d 60 vmh vml 61 vmh+1d vml+1d 62 vmh+2d vml+2d | | | 126 vmh+62d vml+62d 127 vmh+63d vml+63d -if vmh-xd or vml-xd is less than 0d, it become s 0d. -ifvmh+xd or vml+xd is large than 100d, it beco mes 100d. -vmf[6:0] are stored in nv memory to contrast. -the nvm need be used in 1 st parameter of vmofctr (c7h) default status default value vmf[5:0] power mode on sequence 3ch s/w reset 3ch h/w reset 3ch
ST7773 ver. 2.0 2008-07-07 110 10.2.15 step ctr (c9h): step1/2/4 booster frequency control beh rdvmof (read the vcom offset value nv memory) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rdvmof 0 1 - 1 1 0 0 1 0 0 1 (c9h) 1st parameter 1 1 - dual_en step_div_en 1 0 0 cp1_freq_sel[2:0] a4h 2nd parameter 1 1 - nw_mode 0 0 0 0 cp2_freq_sel[2:0] 04h 2nd parameter 1 1 - 0 0 0 0 0 cp4_freq_sel[2:0] 04h note: - dont care description dual_en step1/2/4 booster mode select, default 1(dual mode) step_div_en step1/2/3 clk select osc frequency divid 4 enable,0 (default),1 divid 4 nw_mode select panel type,0=normally white,1=normally black step_div_en cp1_freq_sel[2:0] step-up cycle in booster circuit1 cp2_freq_sel[2:0] step-up cycle in booster circuit 2 0/1 000 0 osc/1024, osc/4096 000 0 osc/1024, osc/4096 0/1 001 1 osc/512, osc/2048 001 1 osc/512, osc/2048 0/1 010 2 osc/256, osc/1024 010 2 osc/256, osc/1024 0/1 011 3 osc/128, osc/512 011 3 osc/128, osc/512 0/1 100 4 osc/64, osc/256 100 4 osc/64, osc/256 0/1 101 5 osc/32, osc/128 101 5 osc/32, osc/128 0/1 110 6 osc/16, osc/64 110 6 osc/16, osc/64 0/1 111 7 osc/8, osc/32 111 7 osc/8, osc/32 step_div_en cp4_freq_sel[2:0] step-up cycle in booster circuit4 0/1 000 0 osc/1024, osc/4096 0/1 001 1 osc/512, osc/2048 0/1 010 2 osc/256, osc/1024 0/1 011 3 osc/128, osc/512 0/1 100 4 osc/64, osc/256 0/1 101 5 osc/32, osc/128 0/1 110 6 osc/16, osc/64 0/1 111 7 osc/8, osc/32 default status default value power on sequence - s/w reset a4h/04h/04h h/w reset a4h/04h/04h
ST7773 ver. 2.0 2008-07-07 111 10.2.16 rd pulse ctr (f4h): adjust read gram timing control function f8h vmofctr (vcom offset control) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) 8-color detect 0 1 - 1 1 1 1 1 0 0 0 (f4h) 1st parameter 1 1 - 0 1 0 1 rd_pulse_width[3:0] 55h note: - dont care, can be set to vddi or dgnd le vel description -this command is used toadjust read gram timing cont rol function default status default value power on sequence 55h s/w reset 55h h/w reset 55h 10.2.17 8-color (f8h): 8 color detect function f8h vmofctr (vcom offset control) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) 8-color detect 0 1 - 1 1 1 1 1 0 0 0 (f8h) 1st parameter 1 1 - 0 0 0 0 0 8-color 0 0 04h note: - dont care, can be set to vddi or dgnd le vel description -this command is used to turn on/off 8-color detect function 1 enable 8-color detect function 0 disable 8-color detect function default status default value power on sequence 04h s/w reset 04h h/w reset 04h
ST7773 ver. 2.0 2008-07-07 112 10.2.18 pwctr6 (fch): power control 6 fch rdvmof (read the vcom offset value nv memory) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) pwctr6 0 1 - 1 1 1 1 1 1 0 0 (fch) 1st parameter 1 1 - 0 0 1 1 1 sapa[2:0] 3ch 2nd parameter 1 1 - 0 1 1 1 1 sapb[2:0] 7ch 2nd parameter 1 1 - 0 0 0 0 0 sapc[2:0] 04h note: - dont care description -adjust the amount of fixed current from the fixed current source in the operational amplifier for the gate driver. -sapa[2:0] set the amount of current in operational amplifier in normal mode. sapa[2:0] amount of current in operational amplifier 000 0 operation of the operational amplifier stops 001 1 small 010 2 medium low 011 3 medium 100 4 medium high 101 5 large low 110 6 large 111 7 large high -sapb[2:0] set the amount of current in operational amplifier in idle mode. sapa[2:0] amount of current in operational amplifier 000 0 operation of the operational amplifier stops 001 1 small 010 2 medium low 011 3 medium 100 4 medium high 101 5 large low 110 6 large 111 7 large high -sapc[2:0] set the amount of current in operational amplifier in partial/full color mode. sapc[2:0] amount of current in operational amplifier 000 0 operation of the operational amplifier stops 001 1 small 010 2 medium low 011 3 medium 100 4 medium high 101 5 large low 110 6 large 111 7 large high default status default value sapa[2:0]/ sapb[2:0]/sapc[2:0] power on sequence - s/w reset 3c/7c/04h h/w reset 3c/7c/04h
ST7773 ver. 2.0 2008-07-07 113 10.2.19 wrid2 (d1h): write id2 value d1h wrid2 (write id2 value) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) wrid2 0 1 - 1 1 0 1 0 0 0 1 (d1h) 1st parameter 1 1 - 1 id26 id25 id24 id23 id22 id21 id20 - note: - dont care description -write 7-bit data of lcd module version to save it to nv memory. -the 1 st parameter id2[6:0] is lcd module version id. default status default value power on sequence - s/w reset - h/w reset - 10.2.20 nvfctr2 (deh): nv memory function controlle r 2 deh nvfctr1 (nv memory function controller 2) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) nvfctr1 0 1 - 1 1 0 1 1 1 1 0 (deh) 1 st parameter 1 1 0 1 0 1 0 1 0 1 75 note: - dont care description 1. eeprom burst read default status default value power on sequence not fixed s/w reset not fixed h/w reset not fixed
ST7773 ver. 2.0 2008-07-07 114 flow chart eeprom burst read mcu write deh parameter1 (75) next mcu command y eeprom cell serial out write to all register n eeprom rdy polling d9h bit0 10.2.21 nvfctr3 (dfh): nv memory function controlle r 3 dfh nvfctr1 (nv memory function controller 3 inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) nvfctr1 0 1 - 1 1 0 1 1 1 1 1 (dfh) 1 st parameter 1 1 - 1 1 0 0 1 0 1 0 ca 2 nd parameter 1 1 - 0 0 0 0 0 0 0 0 00 3 rd parameter 1 1 - 1 0 1 0 1 0 1 0 aa 4 rd parameter 1 1 - 1 0 1 0 0 1 0 1 a5 5 rd parameter 1 1 - 0 1 0 1 1 0 1 0 5a note: - dont care description eeprom write command description 1. eeprom burst write
ST7773 ver. 2.0 2008-07-07 115 default status default value power on sequence not fixed s/w reset not fixed h/w reset not fixed flow chart
ST7773 ver. 2.0 2008-07-07 116 10.2.22 gmctrp1 (e0h): gamma (+polarity) correcti on characteristics setting e0h gmctrp0 (gamma +polarity correction characteristic s setting) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) gmctrp1 0 1 - 1 1 1 0 0 0 0 0 (e0h) 1 st parameter 1 1 - - - vrf0p[5] vrf0p[4] vf0p[3] vrf0p[2] vrf0p[1] vrf0p[0] 2 nd parameter 1 1 - - - vos0p[5] vos0p[4] vos0p[3] vos0p[2] vos0p[1] vos0p[0] 3 rd parameter 1 1 - - - pk0p[5] pk0p[4] pk0p[3] pk0p[2] pk0p[1] pk0p[0] 4 th parameter 1 1 - - - pk1p[5] pk1p[4] pk1p[3] pk1p[2] pk1p[1] pk1p[0] 5 th parameter 1 1 - - - pk2p[5] pk2p[4] pk2p[3] pk2p[2] pk2p[1] pk2p[0] 6 th parameter 1 1 - - - pk3p[5] pk3p[4] pk3p[3] pk3p[2] pk3p[1] pk3p[0] 7 th parameter 1 1 - - - pk4p[5] pk4p[4] pk4p[3] pk4p[2] pk4p[1] pk4p[0] 8 th parameter 1 1 - - - pk5p[5] pk5p[4] pk5p[3] pk5p[2] pk5p[1] pk5p[0] 9 th parameter 1 1 - - - pk6p[5] pk6p[4] pk6p[3] pk6p[2] pk6p[1] pk6p[0] 10 th parameter 1 1 - - - pk7p[5] pk7p[4] pk7p[3] pk7p[2] pk7p[1] pk7p[0] 11 th parameter 1 1 - - - pk8p[5] pk8p[4] pk8p[3] pk8p[2] pk8p[1] pk8p[0] 12 th parameter 1 1 - - - pk9p[5] pk9p[4] pk9p[3] pk9p[2] pk9p[1] pk9p[0] 13 th parameter 1 1 - - - selv0p[5] selv0p[4] selv0p[3] selv0p[2] selv0p[1] selv0p[0] 14 th parameter 1 1 - - - selv1p[5] selv1p[4] selv1p[3] selv1p[2] selv1p[1] selv1p[0] 15 th parameter 1 1 - - - selv62p[5] selv62p[4] selv62p[3] selv62p[2] selv62p[1] selv62p[0] 16 th parameter 1 1 - - - selv63p[5] selv63p[4] selv63p[3] selv63p[2] selv63p[1] selv63p[0] note: - dont care description register group negative polarity set-up contents high level adjustment vrf0p[5:0] variable resistor vrhp selv0p[5:0] the voltage of grayscale number 0 is selected by the 64 to 1 selector selv1p[5:0] the voltage of grayscale number 1 is selected by the 64 to 1 selector pk0p[5:0] the voltage of grayscale number 3 is selected by the 64 to 1 selector pk1p[5:0] the voltage of grayscale number 6 is selected by the 64 to 1 selector pk2p[5:0] the voltage of grayscale number 11 is selected by the 64 to 1 selector pk3p[5:0] the voltage of grayscale number 19 is selected by the 64 to 1 selector pk4p[5:0] the voltage of grayscale number 27 is selected by the 64 to 1 selector pk5p[5:0] the voltage of grayscale number 36 is selected by the 64 to 1 selector pk6p[5:0] the voltage of grayscale number 44 is selected by the 64 to 1 selector pk7p[5:0] the voltage of grayscale number 52 is selected by the 64 to 1 selector pk8p[5:0] the voltage of grayscale number 57 is selected by the 64 to 1 selector pk9p[5:0] the voltage of grayscale number 60 is selected by the 64 to 1 selector selv62p[5:0] the voltage of grayscale number 62 is selected by the 64 to 1 selector mid level adjustment selv63p[5:0] the voltage of grayscale number 63 is selected by the 64 to 1 selector low level adjustment vos0p[5:0] variable resistor vrlp
ST7773 ver. 2.0 2008-07-07 117 10.2.23 gmctrn1 (e1h): gamma -polarity correction characteristics setting e0h gmctrp0 (gamma +polarity correction characteristic s setting) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) gmctrn1 0 1 - 1 1 1 0 0 0 0 1 (e1h) 1 st parameter 1 1 - - - vrf0n[5] vrf0n[4] vf0n[3] vrf0n[2] vrf0n[1] vrf0n[0] 2 nd parameter 1 1 - - - vos0n[5] vos0n[4] vos0n[3] vos0n[2] vos0n[1] vos0n[0] 3 rd parameter 1 1 - - - pk0n[5] pk0n[4] pk0n[3] pk0n[2] pk0n[1] pk0n[0] 4 th parameter 1 1 - - - pk1n[5] pk1n[4] pk1n[3] pk1n[2] pk1n[1] pk1n[0] 5 th parameter 1 1 - - - pk2n[5] pk2n[4] pk2n[3] pk2n[2] pk2n[1] pk2n[0] 6 th parameter 1 1 - - - pk3n[5] pk3n[4] pk3n[3] pk3n[2] pk3n[1] pk3n[0] 7 th parameter 1 1 - - - pk4n[5] pk4n[4] pk4n[3] pk4n[2] pk4n[1] pk4n[0] 8 th parameter 1 1 - - - pk5n[5] pk5n[4] pk5n[3] pk5n[2] pk5n[1] pk5n[0] 9 th parameter 1 1 - - - pk6n[5] pk6n[4] pk6n[3] pk6n[2] pk6n[1] pk6n[0] 10 th parameter 1 1 - - - pk7n[5] pk7n[4] pk7n[3] pk7n[2] pk7n[1] pk7n[0] 11 th parameter 1 1 - - - pk8n[5] pk8n[4] pk8n[3] pk8n[2] pk8n[1] pk8n[0] 12 th parameter 1 1 - - - pk9[5] pk9n[4] pk9n[3] pk9n[2] pk9n[1] pk9n[0] 13 th parameter 1 1 - - - selv0n[5] selv0n[4] selv0n[3] selv0n[2] selv0n[1] selv0n[0] 14 th parameter 1 1 - - - selv1n[5] selv1n[4] selv1n[3] selv1n[2] selv1n[1] selv1n[0] 15 th parameter 1 1 - - - selv62n[5] selv62n[4] selv62n[3] selv62n[2] selv62n[1] selv62n[0] 16 th parameter 1 1 - - - selv63n[5] selv63n[4] selv63n[3] selv63n[2] selv63n[1] selv63n[0] note: - dont care description register group negative polarity set-up contents high level adjustment vrf0n[5:0] variable resistor vrh n selv0n[5:0] the voltage of grayscale number 0 is selected by the 64 to 1 selector selv1n[5:0] the voltage of grayscale number 1 is selected by the 64 to 1 selector pk0n[5:0] the voltage of grayscale number 3 is selected by the 64 to 1 selector pk1n[5:0] the voltage of grayscale number 6 is selected by the 64 to 1 selector pk2n[5:0] the voltage of grayscale number 11 is selected by the 64 to 1 selector pk3n[5:0] the voltage of grayscale number 19 is selected by the 64 to 1 selector pk4n[5:0] the voltage of grayscale number 27 is selected by the 64 to 1 selector pk5n[5:0] the voltage of grayscale number 36 is selected by the 64 to 1 selector pk6n[5:0] the voltage of grayscale number 44 is selected by the 64 to 1 selector pk7n[5:0] the voltage of grayscale number 52 is selected by the 64 to 1 selector pk8n[5:0] the voltage of grayscale number 57 is selected by the 64 to 1 selector pk9n[5:0] the voltage of grayscale number 60 is selected by the 64 to 1 selector selv62n[5:0] the voltage of grayscale number 62 is selected by the 64 to 1 selector mid level adjustment selv63n[5:0] the voltage of grayscale number 63 is selected by the 64 to 1 selector low level adjustment vos0n[5:0] variable resistor vrln
ST7773 ver. 2.0 2008-07-07 118 11. power structure 11.1. driver ic operating voltages specification fig 11.1.1 power booster level vdd=(2.7v~3.3v) agnd=0v vgh(10~16v) avdd(4.8~5.3v) gvdd(3.0~ 5.0v) vcomh(2.5 ~ 5.0v) vcoml(-2.5 ~ 0v) avdd change pump reference voltage internal reference voltage vref vci1 vcl(-2.5 ~ -2.75v) vgl(-13 ~ -5.5v) remark 1. avdd supply to all power source (exclude vgh, vg l) 2. linear range: 0.2v ~ avdd-0.1v (for all output v oltage, but exclude vgh, vgl) 3. above operating voltages is min range.
ST7773 ver. 2.0 2008-07-07 119 11.2 power step1/2/4 circuit 11.2.1 vci1 generate from vref fig. 11.2.1 power booster structure (1)
ST7773 ver. 2.0 2008-07-07 120 11.2.2 external components connection pad name connection rated (min) voltage typical capacitance value vddi vddi (logic power) 6.3v 1.0 uf vdd vdd (analog power) 6.3v 1.0 uf vcc connect to capacitor (max 3v): vcc -------||--- ----- gnd 6.3v 1.0 uf agnd analog ground (connect to gnd) dgnd digital ground (connect to gnd) c23p, c23n connect to capacitor: c23p -------||---- ----c23n 16.0v 1.0 uf c22p, c22n connect to capacitor: c22p -------||---- ----c22n 25.0v 1.0 uf c21p, c22n connect to capacitor: c21p -------||--- -----c21n 6.3v 1.0 uf c12p, c12n connect to capacitor: c12p -------||---- ----c12n 6.3v 1.0 uf c11p, c11n connect to capacitor: c11p -------||---- ----c11n 6.3v 1.0 uf avdd connect to capacitor: avdd -------||-------- g nd 6.3v 1.0 uf vci1 connect to capacitor: avdd -------||-------- g nd 6.3v 1.0 uf vgh connect to capacitor: vgh -------||-------- gnd 25.0v 1.0 uf vgl connect to capacitor: vgl -------||-------- gnd 16.0v 1.0 uf vcl connect to capacitor: vcl -------||-------- gnd 6.3v 1.0 uf vref connect to capacitor: vref -------||-------- g nd(optional) 6.3v 1.0 uf gvdd connect to capacitor: gvdd -------||-------- g nd(optional) 6.3v 1.0 uf vcomh connect to capacitor: vcomh-------||--------- gnd 6.3v 1.0 uf vcoml connect to capacitor: vcoml -------||-------- gnd 6.3v 1.0 uf vgl connect to schottky diode: vgl -------.|-------- gn d 30v schottky diode(note1) note1: leakage current must to be smaller than 20ua when the schottky diode operates at -30~ 85 .
ST7773 ver. 2.0 2008-07-07 121 12. gamma structure 12.1 structure of grayscale amplifier the structure of grayscale amplifier is shown as be low. 16 voltage levels (vin0-vin15) between gvdd an d vgs are determined by the high/ mid/ low level adjustment r egisters. each mid-adjustment level is split into 6 4 levels again by the internal ladder resistor network. as a result, gray scale amplifier generates 64 voltage levels ranging from v0 to v63 and outputs one of 64 levels.
ST7773 ver. 2.0 2008-07-07 122 12.2 ST7773 gamma voltage formula (positive/ negati ve polarity) grayscale voltage formula(positive) voltage formula(negative) 0 vinp0 vinn0 1 vinp1 vinn1 2 vinp2 vinn2 3 vinp3 vinn3 4 v3-(v3-v6)*(11/30) v3-(v3-v6)*(11/30) 5 v3-(v3-v6)*(21/30) v3-(v3-v6)*(21/30) 6 vinp4 vinn4 7 v6-(v6-v11)*(7/30) v6-(v6-v11)*(7/30) 8 v6-(v6-v11)*(14/30) v6-(v6-v11)*(14/30) 9 v6-(v6-v11)*(20/30) v6-(v6-v11)*(20/30) 10 v6-(v6-v11)*(25/30) v6-(v6-v11)*(25/30) 11 vinp5 vinn5 12 v11-(v11-v19)*(4/32) v11-(v11-v19)*(4/32) 13 v11-(v11-v19)*(8/32) v11-(v11-v19)*(8/32) 14 v11-(v11-v19)*(12/32) v11-(v11-v19)*(12/32) 15 v11-(v11-v19)*(16/32) v11-(v11-v19)*(16/32) 16 v11-(v11-v19)*(20/32) v11-(v11-v19)*(20/32) 17 v11-(v11-v19)*(24/32) v11-(v11-v19)*(24/32) 18 v11-(v11-v19)*(28/32) v11-(v11-v19)*(28/32) 19 vinp6 vinn6 20 v19-(v19-v27)*(4/32) v19-(v19-v27)*(4/32) 21 v19-(v19-v27)*(8/32) v19-(v19-v27)*(8/32) 22 v19-(v19-v27)* (12/32) v19-(v19-v27)* (12/32) 23 v19-(v19-v27)* (1632/) v19-(v19-v27)* (1632/) 24 v19-(v19-v27)* (20/32) v19-(v19-v27)* (20/32) 25 v19-(v19-v27)* (24/32) v19-(v19-v27)* (24/32) 26 v19-(v19-v27)* (28/32) v19-(v19-v27)* (28/32) 27 vinp7 vinn7 28 v27-(v27-v36)* (4/36) v27-(v27-v36)* (4/36) 29 v27-(v27-v36)* (8/36) v27-(v27-v36)* (8/36) 30 v27-(v27-v36)* (12/36) v27-(v27-v36)* (12/36) 31 v27-(v27-v36)* (16/36) v27-(v27-v36)* (16/36) 32 v27-(v27-v36)* (20/36) v27-(v27-v36)* (20/36) 33 v27-(v27-v36)* (24/36) v27-(v27-v36)* (24/36) 34 v27-(v27-v36)* (28/36) v27-(v27-v36)* (28/36) 35 v27-(v27-v36)* (32/36) v27-(v27-v36)* (32/36) 36 vinp8 vinn8 37 v36-(v36-v44)*(4/32) v36-(v36-v44)*(4/32) 38 v36-(v36-v44)*(8/32) v36-(v36-v44)*(8/32) 39 v36-(v36-v44)*(12/32) v36-(v36-v44)*(12/32) 40 v36-(v36-v44)*(16/32) v36-(v36-v44)*(16/32) 41 v36-(v36-v44)*(20/32) v36-(v36-v44)*(20/32) 42 v36-(v36-v44)*(24/32) v36-(v36-v44)*(24/32) 43 v36-(v36-v44)*(28/32) v36-(v36-v44)*(28/32) 44 vinp9 vinn9 45 v44-(v44-v52)*(4/32) v44-(v44-v52)*(4/32) 46 v44-(v44-v52)*(8/32) v44-(v44-v52)*(8/32) 47 v44-(v44-v52)*(12/32) v44-(v44-v52)*(12/32) 48 v44-(v44-v52)*(16/32) v44-(v44-v52)*(16/32) 49 v44-(v44-v52)*(20/32) v44-(v44-v52)*(20/32) 50 v44-(v44-v52)*(24/32) v44-(v44-v52)*(24/32) 51 v44-(v44-v52)*(28/32) v44-(v44-v52)*(28/32) 52 vinp10 vinn10 53 v52-(v52-v57)*(5/30) v52-(v52-v57)*(5/30) 54 v52-(v52-v57)*(11/30) v52-(v52-v57)*(11/30)
ST7773 ver. 2.0 2008-07-07 123 55 v52-(v52-v57)*(17/30) v52-(v52-v57)*(17/30) 56 v52-(v52-v57)*(23/30) v52-(v52-v57)*(23/30) 57 vinp11 vinn11 58 v57-(v57-v60)*(8/30) v57-(v57-v60)*(8/30) 59 v57-(v57-v60)*(18/30) v57-(v57-v60)*(18/30) 60 vinp12 vinn12 61 vinp13 vinn13 62 vinp14 vinn14 63 vinp15 vinn15
ST7773 ver. 2.0 2008-07-07 124 13. example connection with panel direction and dif ferent resolution case 1: (this is default case) - 1 st pixel is at left top of the panel - rgb filter order = r g b - direction default setting (h/w) smx = 0 smy = 0 srgb = 0 s1 = filter r s2 = filter g s3 = filter b - display direction control (s/w) - x-mirror control by mx - y-mirror control by my - xy-exchange control by mv 01h 02h------------ aeh aeh g1 g2 g3 | g4 | | | | | | | | | | | | | | | | | | | | g217 g218 g219 g220 00h afh ST7773 (bump down) ic (bump down) lcd front side cf glass tft glass case 2: - 1 st pixel is at left top of the panel - rgb filter order = b g r - direction default setting (h/w) smx = 0 smy = 0 srgb = 1 s1 = filter r s2 = filter g s3 = filter b - display direction control (s/w) - x-mirror control by mx - y-mirror control by my - xy-exchange control by mv 01h 02h------------ aeh aeh g1 g2 g3 | g4 | | | | | | | | | | | | | | | | | | | | g217 g218 g219 g220 00h afh ST7773 (bump down) ic (bump down) lcd front side cf glass tft glass
ST7773 ver. 2.0 2008-07-07 125 case 3: - 1 st pixel is at righ bottom of the panel - rgb filter order = r g b case 4: - 1 st pixel is at righ bottom of the panel - rgb filter order = b g r - direction default setting (h/w) smx = 1 smy = 1 srgb = 1 s1 = filter r s2 = filter g s3 = filter b - display direction control (s/w) - x-mirror control by mx - y-mirror control by my - xy-exchange control by mv 01h 02h------------ aeh aeh g1 g2 g3 | g4 | | | | | | | | | | | | | | | | | | | | g217 g218 g219 g220 00h afh ST7773 (bump down) ic (bump down) lcd front side cf glass tft glass
ST7773 ver. 2.0 2008-07-07 126 13.3 microprocessor interface applications 13.3.1 8080-series mcu interface for 8-bit data bus (im1, im0=00) note: im2=0, spi i/f im2=1, mcu i/f host ST7773 resx te d/cx(scl) wrx rdx d7 to d0 "00" resx te d/cx wrx rdx d7 to d0 d15 to d8 d17 to d16 im1,im0 im2 "00" "00" "1" fig.13.3.1 8080-series mcu interface for 8-bit data bus csx csx 13.3.2 8080-series mcu interface for 16-bit data bu s (im1, im0=01) note: im2=0, spi i/f im2=1, mcu i/f host ST7773 resx te d/cx(scl) wrx rdx d7 to d0 resx te d/cx wrx rdx d7 to d0 d15 to d8 d17 to d16 im1,im0 im2 "00" "00" "1" fig.13.3.2 8080-series mcu interface for 16-bit dat a bus csx d15 to d8 csx
ST7773 ver. 2.0 2008-07-07 127 13.3.3 8080-series mcu interface for 9-bit data bus (im1, im0=10) note: im2=0, spi i/f im2=1, mcu i/f host ST7773 resx te d/cx(scl) wrx rdx d8 to d0 resx te d/cx wrx rdx d8 to d0 d15 to d9 d17 to d16 im1,im0 im2 "00" "10" "1" fig.13.3.3 8080-series mcu interface for 9-bit data bus csx "00" csx 13.3.4 8080-series mcu interface for 18-bit data bu s (im1, im0=11) note: im2=0, spi i/f im2=1, mcu i/f host ST7773 resx te d/cx(scl) wrx rdx d7 to d0 resx te d/cx wrx rdx d7 to d0 d15 to d8 d17 to d16 im1,im0 im2 "11" "1" fig.13.3.4 8080-series mcu interface for 18-bit dat a bus csx d17 to d16 d15 to d8 csx 13.3.5 3-line series interface(im2=0) note: im2=0, spi i/f im2=1, mcu i/f host ST7773 resx te scl "1" "1" d7 to d1 "00" resx te d/cx(scl) wrx rdx d7 to d1 d15 to d8 d17 to d16 im1,im0 im2 "00" "00" "0" fig.13.3.5 spi 3-lie interface spi-csx csx sda d0(sda)
ST7773 ver. 2.0 2008-07-07 128 ST7773 serial specification revision history version date description 1.x 2008/01/-- preliminary 2.0 2008/07/04 mass prooduction release

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